11#include "irx_imports.h"
13#define MODNAME "clearspu"
16static char buf_zero[0xC00];
18static void _spu2_config_initialize(
void);
19static void _spu2_config_initialize_typically(
void);
20static void start_inner2(
void);
21static int do_spu_intr(
void *userdata);
22static void SpuStart(
void);
23static void spu_init_(
void);
24static int do_dma_finish(
void *userdata);
25static void do_dma_stop(
int which_core);
26static int do_dma_get_status(
int which_core);
27static void do_dma_start(
void *addr,
int size,
int which_core);
28static void do_spu_wait(
void);
30int _start(
int argc,
char *argv[])
44 _spu2_config_initialize();
46 _spu2_config_initialize_typically();
51 memset(buf_zero, 0,
sizeof(buf_zero));
52 for ( i = 0; i < 2; i += 1 )
55 do_dma_start(buf_zero,
sizeof(buf_zero), i);
57 while ( do_dma_get_status(0) && do_dma_get_status(1) )
62 printf(
"clearspu: completed\n");
64 return MODULE_NO_RESIDENT_END;
67static void spu2_config_iop_(
void)
69 *((vu32 *)0xBF801404) = 0xBF900000;
70 *((vu32 *)0xBF80140C) = 0xBF900800;
71 *((vu32 *)0xBF8010F0) |= 0x80000u;
72 *((vu32 *)0xBF801570) |= 8u;
73 *((vu32 *)0xBF801014) = 0x200B31E1;
74 *((vu32 *)0xBF801414) = 0x200B31E1;
77static void spu2_config_SPDIF_(
void)
80 *((vu16 *)0xBF9007C6) = 2304;
81 *((vu16 *)0xBF9007C8) = 512;
82 *((vu16 *)0xBF9007CA) = 8;
85static void _spu2_config_initialize(
void)
91static void _spu2_config_initialize_typically(
void)
94 *((vu16 *)0xBF9007C0) = -16334;
95 *((vu16 *)0xBF90019A) = -16384;
96 *((vu16 *)0xBF90059A) = -16383;
97 *((vu16 *)0xBF900188) = -1;
98 *((vu16 *)0xBF90018A) = 255;
99 *((vu16 *)0xBF900190) = -1;
100 *((vu16 *)0xBF900192) = 255;
101 *((vu16 *)0xBF90018C) = -1;
102 *((vu16 *)0xBF90018E) = 255;
103 *((vu16 *)0xBF900194) = -1;
104 *((vu16 *)0xBF900196) = 255;
105 *((vu16 *)0xBF900588) = -1;
106 *((vu16 *)0xBF90058A) = 255;
107 *((vu16 *)0xBF900590) = -1;
108 *((vu16 *)0xBF900592) = 255;
109 *((vu16 *)0xBF90058C) = -1;
110 *((vu16 *)0xBF90058E) = 255;
111 *((vu16 *)0xBF900594) = -1;
112 *((vu16 *)0xBF900596) = 255;
113 *((vu16 *)0xBF900198) = 4080;
114 *((vu16 *)0xBF900598) = 4092;
115 *((vu16 *)0xBF900760) = 0;
116 *((vu16 *)0xBF900762) = 0;
117 *((vu16 *)0xBF900788) = 0;
118 *((vu16 *)0xBF90078A) = 0;
119 *((vu16 *)0xBF900764) = 0;
120 *((vu16 *)0xBF900766) = 0;
121 *((vu16 *)0xBF90078C) = 0;
122 *((vu16 *)0xBF90078E) = 0;
123 *((vu16 *)0xBF90033C) = 14;
124 *((vu16 *)0xBF90073C) = 15;
125 *((vu16 *)0xBF900768) = 0;
126 *((vu16 *)0xBF90076A) = 0;
127 *((vu16 *)0xBF900790) = 0x7FFF;
128 *((vu16 *)0xBF900792) = 0x7FFF;
129 *((vu16 *)0xBF90076C) = 0;
130 *((vu16 *)0xBF90076E) = 0;
131 *((vu16 *)0xBF900794) = 0;
132 *((vu16 *)0xBF900796) = 0;
135static void start_inner2(
void)
142static int do_spu_intr(
void *userdata)
149static int intr_flag_spu12[2] = {0, 1};
151static void SpuStart(
void)
163static void spu_init_(
void)
171 spu_RXX_ = (vu16 *)0xBF900000;
172 spu_sys_pcr_ = (vu32 *)0xBF8010F0;
173 *spu_sys_pcr_ |= 0xB0000u;
181 for ( i = 0; i < 2; i += 1 )
189 spu_RXX_[512 * i + 205] = 0;
193 spu_RXX_[512 * i + 205] = 0x8000;
197 v3 = &spu_RXX_[20 * i];
198 v4 = &spu_RXX_[512 * i];
202 while ( (v4[418] & 0x7FF) != 0 )
206 printf(
"SPU:T/O [%s]\n",
"wait (reset)");
211 v6 = &spu_RXX_[512 * i];
217static int do_dma_finish(
void *userdata)
221 which_core = (*(u32 *)userdata) & 0xFF;
223 *(vu16 *)((which_core << 10) + 0xBF90019A) &= 0xFFCFu;
224 *(vu16 *)((which_core << 10) + 0xBF900198) &= 0xFF3Fu;
225 *(vu16 *)((which_core << 10) + 0xBF9001B0) = 0;
231static void do_dma_stop(
int which_core)
233 *(vu16 *)((which_core << 10) + 0xBF90019A) &= 0xFFCFu;
234 *(vu16 *)((which_core << 10) + 0xBF9001B0) = 0;
237static int do_dma_get_status(
int which_core)
240 if ( *(vu16 *)((which_core << 10) + 0xBF9001B0) )
241 return (*(vu32 *)(1088 * which_core + 0xBF8010C0)) & 0xFFFFFF;
245static void do_dma_start(
void *addr,
int size,
int which_core)
248 *(vu16 *)((which_core << 10) + 0xBF90019A) &= 0xFFCFu;
249 *(vu16 *)((which_core << 10) + 0xBF9001A8) = 0;
250 *(vu16 *)((which_core << 10) + 0xBF9001AA) = 0;
251 *(vu16 *)((which_core << 10) + 0xBF9001B0) = 1 << which_core;
252 *(vu32 *)(1088 * which_core + 0xBF8010C0) = (uiptr)addr;
253 *(vu16 *)(1088 * which_core + 0xBF8010C4) = 16;
254 *(vu16 *)(1088 * which_core + 0xBF8010C6) = size / 64 + (size % 64 > 0);
255 *(vu32 *)(1088 * which_core + 0xBF8010C8) = 16777729;
258static void do_spu_wait(
void)
264 for ( i = 0; i < 80; ++i )
266 __asm__ __volatile__(
"" :
"+g"(v1) : :);
int RegisterIntrHandler(int irq, int mode, int(*handler)(void *), void *arg)
int ReleaseIntrHandler(int irq)
int DisableIntr(int irq, int *res)