PS2SDK
PS2 Homebrew Libraries
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s147ctrl.c
1/*
2# _____ ___ ____ ___ ____
3# ____| | ____| | | |____|
4# | ___| |____ ___| ____| | \ PS2DEV Open Source Project.
5#-----------------------------------------------------------------------
6# Copyright ps2dev - http://www.ps2dev.org
7# Licenced under Academic Free License version 2.0
8# Review ps2sdk README & LICENSE files for further details.
9*/
10
11#include "irx_imports.h"
12#include <errno.h>
13#include <loadcore.h>
14#include <s147_mmio_hwport.h>
15#include <sys/fcntl.h>
16
17IRX_ID("S147CTRL", 2, 8);
18// Text section hash:
19// 0cc30d14ced9b7ccec282df9d56d0bf4
20
21typedef struct watchdog_info_
22{
23 int g_watchdog_started;
24 iop_sys_clock_t g_watchdog_clock;
25} watchdog_info_t;
26
27typedef struct sram_drv_privdata_
28{
29 u32 m_curpos;
30 u32 m_maxpos;
31} sram_drv_privdata_t;
32
33static void setup_ac_delay_regs(void);
34static int setup_ctrl_ioman_drv(const char *devpfx, const char *devname);
35static unsigned int watchdog_alarm_cb(void *userdata);
36static int ctrl_drv_op_open(const iop_file_t *f, const char *name, int flags);
37static int ctrl_drv_op_close(iop_file_t *f);
38static int ctrl_drv_op_read(const iop_file_t *f, void *ptr, int size);
39static int ctrl_drv_op_write(const iop_file_t *f, void *ptr, int size);
40static int create_ctrl_sema(void);
41static int ctrl_do_rtc_read(u32 *rtcbuf);
42static int ctrl_do_rtc_read_inner(int flgcnt, int flgmsk);
43static int ctrl_do_rtc_write(const u32 *rtcbuf);
44static void ctrl_do_rtc_write_inner(int inflg, int flgcnt, int flgmsk);
45static int setup_sram_ioman_drv(const char *devpfx, const char *devname);
46static int sram_drv_op_open(iop_file_t *f, const char *name, int flags);
47static int sram_drv_op_close(iop_file_t *f);
48static int sram_drv_op_read(iop_file_t *f, void *ptr, int size);
49static int sram_drv_op_write(iop_file_t *f, void *ptr, int size);
50static int sram_drv_op_lseek(iop_file_t *f, int offset, int mode);
51static int do_rpc_start1(void);
52static void rpc_thread1(void *userdata);
53static void *rpc_1470000_handler(int fno, void *buffer, int length);
54static void *rpc_1470001_handler(int fno, void *buffer, int length);
55static void *rpc_1470002_handler(int fno, void *buffer, int length);
56static void *rpc_1470003_handler(int fno, void *buffer, int length);
57static int do_rpc_start2(void);
58static void rpc_thread2(void *userdata);
59static void *rpc_1470200_handler(int fno, void *buffer, int length);
60static void *rpc_1470201_handler(int fno, void *buffer, int length);
61
62// Unofficial: merge callbacks that use the same return value
63IOMAN_RETURN_VALUE_IMPL(0);
64
65static iop_device_ops_t g_ops_ctrl_ioman = {
66 IOMAN_RETURN_VALUE(0),
67 IOMAN_RETURN_VALUE(0),
68 IOMAN_RETURN_VALUE(0),
69 (void *)&ctrl_drv_op_open,
70 (void *)&ctrl_drv_op_close,
71 (void *)&ctrl_drv_op_read,
72 (void *)&ctrl_drv_op_write,
73 IOMAN_RETURN_VALUE(0),
74 IOMAN_RETURN_VALUE(0),
75 IOMAN_RETURN_VALUE(0),
76 IOMAN_RETURN_VALUE(0),
77 IOMAN_RETURN_VALUE(0),
78 IOMAN_RETURN_VALUE(0),
79 IOMAN_RETURN_VALUE(0),
80 IOMAN_RETURN_VALUE(0),
81 IOMAN_RETURN_VALUE(0),
82 IOMAN_RETURN_VALUE(0),
83};
84// Unofficial: move to bss
85static int g_rpc_started;
86// Unofficial: move to bss
87static int g_watchdog_count_1;
88// Unofficial: move to bss
89static char g_watchdog_flag_1;
90// Unofficial: move to bss
91static u32 g_max_timer_counter;
92static iop_device_ops_t g_ops_sram_ioman = {
93 IOMAN_RETURN_VALUE(0),
94 IOMAN_RETURN_VALUE(0),
95 IOMAN_RETURN_VALUE(0),
96 (void *)&sram_drv_op_open,
97 (void *)&sram_drv_op_close,
98 (void *)&sram_drv_op_read,
99 (void *)&sram_drv_op_write,
100 (void *)&sram_drv_op_lseek,
101 IOMAN_RETURN_VALUE(0),
102 IOMAN_RETURN_VALUE(0),
103 IOMAN_RETURN_VALUE(0),
104 IOMAN_RETURN_VALUE(0),
105 IOMAN_RETURN_VALUE(0),
106 IOMAN_RETURN_VALUE(0),
107 IOMAN_RETURN_VALUE(0),
108 IOMAN_RETURN_VALUE(0),
109 IOMAN_RETURN_VALUE(0),
110};
111static iop_device_t g_drv_ctrl_ioman;
112static int g_rtc_flag;
113static int g_timer_id;
114static iop_sema_t g_ctrl_sema_param;
115static int g_ctrl_sema_id;
116static iop_device_t g_drv_sram_ioman;
117static int g_rpc1_buf[8];
118static int g_rpc2_buf[260];
119static watchdog_info_t g_watchdog_info;
120
121int _start(int ac, char **av)
122{
123 (void)ac;
124 (void)av;
125 Kprintf("\n");
126 Kprintf("s147ctrl.irx: System147 Control/SRAM Driver v%d.%d\n", 2, 8);
127 setup_ac_delay_regs();
128 if ( setup_ctrl_ioman_drv("ctrl", "Ctrl") < 0 )
129 {
130 Kprintf("s147ctrl.irx: Ctrl initialize failed\n");
131 return MODULE_NO_RESIDENT_END;
132 }
133 // cppcheck-suppress knownConditionTrueFalse
134 if ( setup_sram_ioman_drv("sram", "SRAM") < 0 )
135 {
136 Kprintf("s147ctrl.irx: Sram initialize failed\n");
137 return MODULE_NO_RESIDENT_END;
138 }
139 return MODULE_RESIDENT_END;
140}
141
142static void setup_ac_delay_regs(void)
143{
144 SetAcMemDelayReg(0x261A2122);
145 SetAcIoDelayReg(0xA61A0166);
146}
147
148static int setup_ctrl_ioman_drv(const char *devpfx, const char *devname)
149{
150 g_watchdog_info.g_watchdog_started = 1;
151 USec2SysClock(0x4E20, &g_watchdog_info.g_watchdog_clock);
152 SetAlarm(&g_watchdog_info.g_watchdog_clock, watchdog_alarm_cb, &g_watchdog_info);
153 if ( create_ctrl_sema() < 0 )
154 return -1;
155 g_drv_ctrl_ioman.name = devpfx;
156 g_drv_ctrl_ioman.type = IOP_DT_FS;
157 g_drv_ctrl_ioman.version = 0;
158 g_drv_ctrl_ioman.desc = devname;
159 g_drv_ctrl_ioman.ops = &g_ops_ctrl_ioman;
160 DelDrv(devpfx);
161 AddDrv(&g_drv_ctrl_ioman);
162 return 0;
163}
164
165static unsigned int watchdog_alarm_cb(void *userdata)
166{
167 int state;
168 u8 unk34_tmp;
169 watchdog_info_t *wdi;
170 USE_S147_DEV9_MEM_MMIO();
171 USE_S147LINK_DEV9_MEM_MMIO();
172
173 wdi = (watchdog_info_t *)userdata;
174 if ( wdi->g_watchdog_started != 1 )
175 {
176 s147_dev9_mem_mmio->m_led = 3;
177 return 0;
178 }
179 CpuSuspendIntr(&state);
180 s147link_dev9_mem_mmio->m_watchdog_flag_unk34 = 0;
181 unk34_tmp = s147link_dev9_mem_mmio->m_watchdog_flag_unk34;
182 CpuResumeIntr(state);
183 if ( unk34_tmp == 0x3E )
184 {
185 s147_dev9_mem_mmio->m_watchdog_flag2 = 0;
186 // Unofficial: add 1 here
187 s147_dev9_mem_mmio->m_led = g_watchdog_flag_1 + 1;
188 g_watchdog_flag_1 = ((((unsigned int)g_watchdog_count_1 >> 3) & 1) != 0) ? 1 : 0;
189 g_watchdog_count_1 += 1;
190 }
191 return wdi->g_watchdog_clock.lo;
192}
193
194static int ctrl_drv_op_open(const iop_file_t *f, const char *name, int flags)
195{
196 int state;
197
198 (void)flags;
199 if ( f->unit != 99 )
200 return 0;
201 if ( !strcmp(name, "watchdog-start") )
202 {
203 Kprintf("s147ctrl.irx: wdt-start\n");
204 CpuSuspendIntr(&state);
205 g_watchdog_info.g_watchdog_started = 1;
206 CpuResumeIntr(state);
207 }
208 else if ( !strcmp(name, "watchdog-stop") )
209 {
210 Kprintf("s147ctrl.irx: wdt-stop\n");
211 CpuSuspendIntr(&state);
212 g_watchdog_info.g_watchdog_started = 0;
213 CpuResumeIntr(state);
214 }
215 else if ( !strcmp(name, "rpcserv-start") )
216 {
217 Kprintf("s147ctrl.irx: rpcserv-start\n");
218 if ( !g_rpc_started )
219 {
220 do_rpc_start1();
221 do_rpc_start2();
222 CpuSuspendIntr(&state);
223 g_rpc_started = 1;
224 CpuResumeIntr(state);
225 }
226 }
227 return 0;
228}
229
230static int ctrl_drv_op_close(iop_file_t *f)
231{
232 (void)f;
233 return 0;
234}
235
236static int ctrl_drv_op_read(const iop_file_t *f, void *ptr, int size)
237{
238 int unit;
239 int retres;
240 USE_S147_DEV9_MEM_MMIO();
241
242 unit = f->unit;
243 switch ( unit )
244 {
245 case 4:
246 if ( size != 0x1C )
247 return -EINVAL;
248 retres = ctrl_do_rtc_read(ptr);
249 if ( retres < 0 )
250 Kprintf("s147ctrl.irx: RTC Read failed (%d)\n", retres);
251 return retres;
252 case 12:
253 if ( size != 2 )
254 return -EINVAL;
255 *(u8 *)ptr = s147_dev9_mem_mmio->m_security_unlock_set1;
256 *((u8 *)ptr + 1) = s147_dev9_mem_mmio->m_security_unlock_set2;
257 return 2;
258 default:
259 if ( size != 1 )
260 return -EINVAL;
261 *(u8 *)ptr = *(u8 *)(unit + 0xB0000000);
262 return 1;
263 }
264}
265
266static int ctrl_drv_op_write(const iop_file_t *f, void *ptr, int size)
267{
268 int unit;
269 int retres;
270 USE_S147_DEV9_MEM_MMIO();
271
272 unit = f->unit;
273 switch ( unit )
274 {
275 case 4:
276 if ( size != 0x1C )
277 return -EINVAL;
278 retres = ctrl_do_rtc_write(ptr);
279 if ( retres < 0 )
280 Kprintf("s147ctrl.irx: RTC Write failed (%d)\n", retres);
281 return retres;
282 case 12:
283 if ( size != 2 )
284 return -EINVAL;
285 s147_dev9_mem_mmio->m_security_unlock_set1 = *(u8 *)ptr;
286 s147_dev9_mem_mmio->m_security_unlock_set2 = *((u8 *)ptr + 1);
287 return 2;
288 default:
289 if ( size != 1 )
290 return -EINVAL;
291 *(u8 *)(unit + 0xB0000000) = *(u8 *)ptr;
292 return 1;
293 }
294}
295
296static int create_ctrl_sema(void)
297{
298 g_ctrl_sema_param.initial = 1;
299 g_ctrl_sema_param.max = 1;
300 g_ctrl_sema_param.attr = SA_THPRI;
301 g_ctrl_sema_id = CreateSema(&g_ctrl_sema_param);
302 if ( g_ctrl_sema_id < 0 )
303 {
304 Kprintf("s147ctrl.irx: CreateSema error (%d)\n", g_ctrl_sema_id);
305 return -1;
306 }
307 return 0;
308}
309
310static int ctrl_do_rtc_read(u32 *rtcbuf)
311{
312 USE_S147_DEV9_MEM_MMIO();
313
314 WaitSema(g_ctrl_sema_id);
315 g_timer_id = AllocHardTimer(1, 0x20, 1);
316 if ( g_timer_id < 0 )
317 return g_timer_id;
318 // Unofficial: omit SetupHardTimer/StartHardTimer
319 g_max_timer_counter = 0x40;
320 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
321 ;
322 g_max_timer_counter += 0x40;
323 s147_dev9_mem_mmio->m_rtc_flag = 1;
324 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
325 ;
326 g_max_timer_counter += 0x40;
327 s147_dev9_mem_mmio->m_rtc_flag = 9;
328 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
329 ;
330 g_max_timer_counter += 0x40;
331 rtcbuf[6] = ctrl_do_rtc_read_inner(8, 0x7F);
332 rtcbuf[5] = ctrl_do_rtc_read_inner(8, 0x7F);
333 rtcbuf[4] = ctrl_do_rtc_read_inner(8, 0x3F);
334 rtcbuf[3] = ctrl_do_rtc_read_inner(4, 7);
335 rtcbuf[2] = ctrl_do_rtc_read_inner(8, 0x3F);
336 rtcbuf[1] = ctrl_do_rtc_read_inner(8, 0x1F);
337 *rtcbuf = ctrl_do_rtc_read_inner(8, 0xFF);
338 s147_dev9_mem_mmio->m_rtc_flag = 1;
339 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
340 ;
341 g_max_timer_counter += 0x40;
342 s147_dev9_mem_mmio->m_rtc_flag = 1;
343 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
344 ;
345 g_max_timer_counter += 0x40;
346 // Unofficial: omit StopHardTimer
347 FreeHardTimer(g_timer_id);
348 g_max_timer_counter = 0;
349 SignalSema(g_ctrl_sema_id);
350 return 0x1C;
351}
352
353static int ctrl_do_rtc_read_inner(int flgcnt, int flgmsk)
354{
355 int i;
356 USE_S147_DEV9_MEM_MMIO();
357
358 g_rtc_flag = 0;
359 for ( i = 0; i < flgcnt; i += 1 )
360 {
361 s147_dev9_mem_mmio->m_rtc_flag = 0xB;
362 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
363 ;
364 g_max_timer_counter += 0x40;
365 g_rtc_flag |= (s147_dev9_mem_mmio->m_rtc_flag & 1) << i;
366 s147_dev9_mem_mmio->m_rtc_flag = 9;
367 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
368 ;
369 g_max_timer_counter += 0x40;
370 }
371 return g_rtc_flag & flgmsk;
372}
373
374static int ctrl_do_rtc_write(const u32 *rtcbuf)
375{
376 USE_S147_DEV9_MEM_MMIO();
377
378 WaitSema(g_ctrl_sema_id);
379 g_timer_id = AllocHardTimer(1, 0x20, 1);
380 if ( g_timer_id < 0 )
381 return g_timer_id;
382 // Unofficial: omit SetupHardTimer/StartHardTimer
383 g_max_timer_counter = 0x40;
384 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
385 ;
386 g_max_timer_counter += 0x40;
387 s147_dev9_mem_mmio->m_rtc_flag = 5;
388 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
389 ;
390 g_max_timer_counter += 0x40;
391 s147_dev9_mem_mmio->m_rtc_flag = 0xD;
392 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
393 ;
394 g_max_timer_counter += 0x40;
395 ctrl_do_rtc_write_inner(rtcbuf[6], 8, 0x7F);
396 ctrl_do_rtc_write_inner(rtcbuf[5], 8, 0x7F);
397 ctrl_do_rtc_write_inner(rtcbuf[4], 8, 0x3F);
398 ctrl_do_rtc_write_inner(rtcbuf[3], 4, 7);
399 ctrl_do_rtc_write_inner(rtcbuf[2], 8, 0x3F);
400 ctrl_do_rtc_write_inner(rtcbuf[1], 8, 0x1F);
401 ctrl_do_rtc_write_inner(*rtcbuf, 8, 0xFF);
402 s147_dev9_mem_mmio->m_rtc_flag = 5;
403 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
404 ;
405 g_max_timer_counter += 0x40;
406 s147_dev9_mem_mmio->m_rtc_flag = 1;
407 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
408 ;
409 g_max_timer_counter += 0x40;
410 // Unofficial: omit StopHardTimer
411 FreeHardTimer(g_timer_id);
412 g_max_timer_counter = 0;
413 SignalSema(g_ctrl_sema_id);
414 return 0x1C;
415}
416
417static void ctrl_do_rtc_write_inner(int inflg, int flgcnt, int flgmsk)
418{
419 int i;
420 unsigned int xval;
421 USE_S147_DEV9_MEM_MMIO();
422
423 xval = inflg & flgmsk;
424 for ( i = 0; i < flgcnt; i += 1 )
425 {
426 s147_dev9_mem_mmio->m_rtc_flag = (xval & 1) | 0xC;
427 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
428 ;
429 g_max_timer_counter += 0x40;
430 s147_dev9_mem_mmio->m_rtc_flag = (xval & 1) | 0xE;
431 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
432 ;
433 g_max_timer_counter += 0x40;
434 xval >>= 1;
435 }
436 s147_dev9_mem_mmio->m_rtc_flag = (xval & 1) | 0xC;
437 while ( GetTimerCounter(g_timer_id) < g_max_timer_counter )
438 ;
439 g_max_timer_counter += 0x40;
440}
441
442static int setup_sram_ioman_drv(const char *devpfx, const char *devname)
443{
444 g_drv_sram_ioman.name = devpfx;
445 g_drv_sram_ioman.type = IOP_DT_FS;
446 g_drv_sram_ioman.version = 0;
447 g_drv_sram_ioman.desc = devname;
448 g_drv_sram_ioman.ops = &g_ops_sram_ioman;
449 DelDrv(devpfx);
450 AddDrv(&g_drv_sram_ioman);
451 return 0;
452}
453
454static int sram_drv_op_open(iop_file_t *f, const char *name, int flags)
455{
456 sram_drv_privdata_t *privdata;
457 int state;
458
459 (void)name;
460 (void)flags;
461 CpuSuspendIntr(&state);
462 f->privdata = AllocSysMemory(ALLOC_FIRST, sizeof(sram_drv_privdata_t), 0);
463 CpuResumeIntr(state);
464 privdata = (sram_drv_privdata_t *)f->privdata;
465 privdata->m_curpos = 0;
466 privdata->m_maxpos = 0x8000;
467 return 0;
468}
469
470static int sram_drv_op_close(iop_file_t *f)
471{
472 int state;
473
474 if ( !f->privdata )
475 return 0;
476 CpuSuspendIntr(&state);
477 FreeSysMemory(f->privdata);
478 CpuResumeIntr(state);
479 f->privdata = 0;
480 return 0;
481}
482
483static int sram_drv_op_read(iop_file_t *f, void *ptr, int size)
484{
485 int sizeb;
486 sram_drv_privdata_t *privdata;
487
488 privdata = (sram_drv_privdata_t *)f->privdata;
489 if ( (s32)privdata->m_curpos >= (s32)privdata->m_maxpos )
490 return 0;
491 sizeb = ((s32)privdata->m_maxpos < (s32)(privdata->m_curpos + size)) ? (privdata->m_maxpos - privdata->m_curpos) :
492 (u32)size;
493 memcpy(ptr, (const void *)(privdata->m_curpos + 0xB0C00000), sizeb);
494 privdata->m_curpos += sizeb;
495 return sizeb;
496}
497
498static int sram_drv_op_write(iop_file_t *f, void *ptr, int size)
499{
500 int sizeb;
501 sram_drv_privdata_t *privdata;
502 USE_S147_DEV9_MEM_MMIO();
503
504 privdata = (sram_drv_privdata_t *)f->privdata;
505 if ( (s32)privdata->m_curpos >= (s32)privdata->m_maxpos )
506 return 0;
507 sizeb = ((s32)privdata->m_maxpos < (s32)(privdata->m_curpos + size)) ? (privdata->m_maxpos - privdata->m_curpos) :
508 (u32)size;
509 s147_dev9_mem_mmio->m_sram_write_flag = 1;
510 memcpy((void *)(privdata->m_curpos + 0xB0C00000), ptr, sizeb);
511 s147_dev9_mem_mmio->m_sram_write_flag = 0;
512 privdata->m_curpos += sizeb;
513 return sizeb;
514}
515
516static int sram_drv_op_lseek(iop_file_t *f, int offset, int mode)
517{
518 sram_drv_privdata_t *privdata;
519
520 privdata = (sram_drv_privdata_t *)f->privdata;
521 switch ( mode )
522 {
523 case SEEK_SET:
524 privdata->m_curpos = offset;
525 break;
526 case SEEK_CUR:
527 privdata->m_curpos += offset;
528 break;
529 case SEEK_END:
530 privdata->m_curpos = privdata->m_maxpos + offset;
531 break;
532 default:
533 return -EINVAL;
534 }
535 if ( (s32)privdata->m_maxpos < (s32)privdata->m_curpos )
536 {
537 privdata->m_curpos = privdata->m_maxpos;
538 return -EINVAL;
539 }
540 return privdata->m_curpos;
541}
542
543static int do_rpc_start1(void)
544{
545 iop_thread_t thparam;
546 int thid;
547
548 thparam.attr = TH_C;
549 thparam.thread = rpc_thread1;
550 thparam.priority = 10;
551 thparam.stacksize = 0x800;
552 thparam.option = 0;
553 thid = CreateThread(&thparam);
554 if ( thid <= 0 )
555 return 1;
556 StartThread(thid, 0);
557 return 0;
558}
559
560static void rpc_thread1(void *userdata)
561{
562 SifRpcDataQueue_t qd;
563 SifRpcServerData_t sd[4];
564
565 (void)userdata;
566 sceSifInitRpc(0);
567 sceSifSetRpcQueue(&qd, GetThreadId());
568 sceSifRegisterRpc(&sd[0], 0x1470000, rpc_1470000_handler, g_rpc1_buf, 0, 0, &qd);
569 sceSifRegisterRpc(&sd[1], 0x1470001, rpc_1470001_handler, g_rpc1_buf, 0, 0, &qd);
570 sceSifRegisterRpc(&sd[2], 0x1470002, rpc_1470002_handler, g_rpc1_buf, 0, 0, &qd);
571 sceSifRegisterRpc(&sd[3], 0x1470003, rpc_1470003_handler, g_rpc1_buf, 0, 0, &qd);
572 sceSifRpcLoop(&qd);
573}
574
575static void *rpc_1470000_handler(int fno, void *buffer, int length)
576{
577 USE_S147_DEV9_MEM_MMIO();
578
579 (void)length;
580 switch ( fno )
581 {
582 case 1:
583 s147_dev9_mem_mmio->m_led = *(u8 *)buffer;
584 *(u32 *)buffer = 0;
585 break;
586 case 2:
587 s147_dev9_mem_mmio->m_security_unlock_unlock = *(u8 *)buffer;
588 *(u32 *)buffer = 0;
589 break;
590 case 3:
591 s147_dev9_mem_mmio->m_unk03 = *(u8 *)buffer;
592 *(u32 *)buffer = 0;
593 break;
594 case 4:
595 s147_dev9_mem_mmio->m_rtc_flag = *(u8 *)buffer;
596 *(u32 *)buffer = 0;
597 break;
598 case 5:
599 s147_dev9_mem_mmio->m_watchdog_flag2 = *(u8 *)buffer;
600 *(u32 *)buffer = 0;
601 break;
602 case 12:
603 s147_dev9_mem_mmio->m_security_unlock_set1 = *(u8 *)buffer;
604 *(u32 *)buffer = 0;
605 break;
606 case 13:
607 s147_dev9_mem_mmio->m_security_unlock_set2 = *(u8 *)buffer;
608 *(u32 *)buffer = 0;
609 break;
610 default:
611 *(u32 *)buffer = -22;
612 break;
613 }
614 return buffer;
615}
616
617static void *rpc_1470001_handler(int fno, void *buffer, int length)
618{
619 USE_S147_DEV9_MEM_MMIO();
620
621 (void)length;
622 switch ( fno )
623 {
624 case 0:
625 *(u8 *)buffer = s147_dev9_mem_mmio->m_unk00;
626 *((u32 *)buffer + 1) = 0;
627 break;
628 case 1:
629 *(u8 *)buffer = s147_dev9_mem_mmio->m_led;
630 *((u32 *)buffer + 1) = 0;
631 break;
632 case 2:
633 *(u8 *)buffer = s147_dev9_mem_mmio->m_security_unlock_unlock;
634 *((u32 *)buffer + 1) = 0;
635 break;
636 case 3:
637 *(u8 *)buffer = s147_dev9_mem_mmio->m_unk03;
638 *((u32 *)buffer + 1) = 0;
639 break;
640 case 4:
641 *(u8 *)buffer = s147_dev9_mem_mmio->m_rtc_flag;
642 *((u32 *)buffer + 1) = 0;
643 break;
644 case 5:
645 *(u8 *)buffer = s147_dev9_mem_mmio->m_watchdog_flag2;
646 *((u32 *)buffer + 1) = 0;
647 break;
648 case 6:
649 *(u8 *)buffer = s147_dev9_mem_mmio->m_unk06;
650 *((u32 *)buffer + 1) = 0;
651 break;
652 case 12:
653 *(u8 *)buffer = s147_dev9_mem_mmio->m_security_unlock_set1;
654 *((u32 *)buffer + 1) = 0;
655 break;
656 case 13:
657 *(u8 *)buffer = s147_dev9_mem_mmio->m_security_unlock_set2;
658 *((u32 *)buffer + 1) = 0;
659 break;
660 default:
661 *(u8 *)buffer = 0;
662 *((u32 *)buffer + 1) = -22;
663 break;
664 }
665 return buffer;
666}
667
668static void *rpc_1470002_handler(int fno, void *buffer, int length)
669{
670 (void)length;
671 *(u32 *)buffer = (fno == 4) ? ctrl_do_rtc_write(buffer) : -22;
672 return buffer;
673}
674
675static void *rpc_1470003_handler(int fno, void *buffer, int length)
676{
677 (void)length;
678 if ( fno != 4 )
679 {
680 *(u32 *)buffer = 0;
681 *((u32 *)buffer + 1) = 0;
682 *((u32 *)buffer + 2) = 0;
683 *((u32 *)buffer + 3) = 0;
684 *((u32 *)buffer + 4) = 0;
685 *((u32 *)buffer + 5) = 0;
686 *((u32 *)buffer + 6) = 0;
687 *((u32 *)buffer + 7) = -22;
688 return buffer;
689 }
690 *((u32 *)buffer + 7) = ctrl_do_rtc_read(buffer);
691 return buffer;
692}
693
694static int do_rpc_start2(void)
695{
696 iop_thread_t thparam;
697 int thid;
698
699 thparam.attr = TH_C;
700 thparam.thread = rpc_thread2;
701 thparam.priority = 10;
702 thparam.stacksize = 0x800;
703 thparam.option = 0;
704 thid = CreateThread(&thparam);
705 if ( thid <= 0 )
706 return 1;
707 StartThread(thid, 0);
708 return 0;
709}
710
711static void rpc_thread2(void *userdata)
712{
713 SifRpcDataQueue_t qd;
714 SifRpcServerData_t sd[2];
715
716 (void)userdata;
717 sceSifInitRpc(0);
718 sceSifSetRpcQueue(&qd, GetThreadId());
719 sceSifRegisterRpc(&sd[0], 0x1470200, rpc_1470200_handler, g_rpc2_buf, 0, 0, &qd);
720 sceSifRegisterRpc(&sd[1], 0x1470201, rpc_1470201_handler, g_rpc2_buf, 0, 0, &qd);
721 sceSifRpcLoop(&qd);
722}
723
724static void *rpc_1470200_handler(int fno, void *buffer, int length)
725{
726 USE_S147_DEV9_MEM_MMIO();
727
728 (void)length;
729 if ( (unsigned int)fno >= 3 )
730 {
731 *(u32 *)buffer = -1;
732 return buffer;
733 }
734 s147_dev9_mem_mmio->m_sram_write_flag = 1;
735 memcpy((void *)(*((u32 *)buffer + 256) + 0xB0C00000), buffer, *((u32 *)buffer + 257));
736 s147_dev9_mem_mmio->m_sram_write_flag = 0;
737 *(u32 *)buffer = 0;
738 return buffer;
739}
740
741static void *rpc_1470201_handler(int fno, void *buffer, int length)
742{
743 (void)length;
744 if ( (unsigned int)fno >= 3 )
745 {
746 memset(buffer, 0, *((u32 *)buffer + 1));
747 *((u32 *)buffer + 256) = -1;
748 return buffer;
749 }
750 memcpy(buffer, (const void *)(*(u32 *)buffer + 0xB0C00000), *((u32 *)buffer + 1));
751 *((u32 *)buffer + 256) = 0;
752 return buffer;
753}
EINVAL
#define EINVAL
Definition errno.h:63
CpuResumeIntr
int CpuResumeIntr(int state)
Definition intrman.c:227
CpuSuspendIntr
int CpuSuspendIntr(int *state)
Definition intrman.c:205
_iop_device::version
unsigned int version
Definition ioman.h:68
_iop_file::privdata
void * privdata
Definition ioman.h:61
_iop_file::unit
int unit
Definition ioman.h:57
_iop_device
Definition ioman.h:64
_iop_device_ops
Definition ioman.h:79
_iop_file
Definition ioman.h:53
s147_mmio_hwport.h
t_SifRpcDataQueue
Definition sifrpc-common.h:154
t_SifRpcServerData
Definition sifrpc-common.h:99
sram_drv_privdata_
Definition s147ctrl.c:28
watchdog_info_
Definition s147ctrl.c:22
_iop_sys_clock
Definition thbase.h:88
_iop_thread
Definition thbase.h:40
iop_sema_t
Definition thsemap.h:39