PS2SDK
PS2 Homebrew Libraries
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s_srmp.c
1/*
2# _____ ___ ____ ___ ____
3# ____| | ____| | | |____|
4# | ___| |____ ___| ____| | \ PS2DEV Open Source Project.
5#-----------------------------------------------------------------------
6# Copyright ps2dev - http://www.ps2dev.org
7# Licenced under Academic Free License version 2.0
8# Review ps2sdk README & LICENSE files for further details.
9*/
10
11#include "libspu2_internal.h"
12
13int SpuSetReverbModeParam(SpuReverbAttr *attr)
14{
15 int b_set_spucnt;
16 int b_r_mode_in_bounds;
17 int b_mode_is_7_to_9_bit0x8;
18 unsigned int mask;
19 int b_mode_is_7_to_9_bit0x10;
20 u32 flagstmp;
22 int b_clear_reverb_work_area;
23
24 b_set_spucnt = 0;
25 b_r_mode_in_bounds = 0;
26 b_mode_is_7_to_9_bit0x8 = 0;
27 b_clear_reverb_work_area = 0;
28 mask = attr->mask;
29 b_mode_is_7_to_9_bit0x10 = 0;
30 entry.flags = 0;
31 if ( mask == 0 )
32 mask = 0xFFFFFFFF;
33 if ( (mask & SPU_REV_MODE) != 0 )
34 {
35 unsigned int mode;
36
37 mode = attr->mode;
38 if ( (mode & SPU_REV_MODE_CLEAR_WA) != 0 )
39 {
40 mode &= ~SPU_REV_MODE_CLEAR_WA;
41 b_clear_reverb_work_area = 1;
42 }
43 b_r_mode_in_bounds = 1;
44 if ( mode >= SPU_REV_MODE_MAX )
45 return SPU_ERROR;
46 _spu_rev_attr.mode = mode;
47 _spu_rev_offsetaddr = SpuGetReverbEndAddr() - (8 * _spu_rev_workareasize[mode] - 2);
48 printf("_spu_rev_offsetaddr %x\n", _spu_rev_offsetaddr);
49 memcpy(&entry, &_spu_rev_param[_spu_rev_attr.mode], sizeof(entry));
50 switch ( _spu_rev_attr.mode )
51 {
52 case SPU_REV_MODE_ECHO:
53 _spu_rev_attr.feedback = 127;
54 _spu_rev_attr.delay = 127;
55 break;
56 case SPU_REV_MODE_DELAY:
57 _spu_rev_attr.feedback = 0;
58 _spu_rev_attr.delay = 127;
59 break;
60 default:
61 _spu_rev_attr.feedback = 0;
62 _spu_rev_attr.delay = 0;
63 break;
64 }
65 }
66 if (
67 ((mask & SPU_REV_DELAYTIME) != 0) && _spu_rev_attr.mode <= SPU_REV_MODE_DELAY
68 && _spu_rev_attr.mode >= SPU_REV_MODE_ECHO )
69 {
70 int delay_converted;
71
72 b_mode_is_7_to_9_bit0x8 = 1;
73 if ( !b_r_mode_in_bounds )
74 {
75 memcpy(&entry, &_spu_rev_param[_spu_rev_attr.mode], sizeof(entry));
76 entry.flags = 0xc011c00;
77 }
78 _spu_rev_attr.delay = attr->delay;
79 entry.mLSAME = (s16)((_spu_rev_attr.delay & 0xFFFF) << 13) / 127 - entry.dAPF1;
80 delay_converted = (_spu_rev_attr.delay << 12) / 127;
81 entry.mRSAME = delay_converted - entry.dAPF2;
82 entry.dLSAME = entry.dRSAME + delay_converted;
83 entry.mLCOMB1 = entry.mRCOMB1 + delay_converted;
84 entry.mRAPF1 = entry.mRAPF2 + delay_converted;
85 entry.mLAPF1 = entry.mLAPF2 + delay_converted;
86 }
87 if (
88 ((mask & SPU_REV_FEEDBACK) != 0) && _spu_rev_attr.mode <= SPU_REV_MODE_DELAY
89 && _spu_rev_attr.mode >= SPU_REV_MODE_ECHO )
90 {
91 b_mode_is_7_to_9_bit0x10 = 1;
92 if ( !b_r_mode_in_bounds )
93 {
94 if ( b_mode_is_7_to_9_bit0x8 )
95 {
96 flagstmp = entry.flags | 0x80;
97 }
98 else
99 {
100 memcpy(&entry, &_spu_rev_param[_spu_rev_attr.mode], sizeof(entry));
101 flagstmp = 128;
102 }
103 entry.flags = flagstmp;
104 }
105 _spu_rev_attr.feedback = attr->feedback;
106 entry.vWALL = 33024 * _spu_rev_attr.feedback / 127;
107 }
108 if ( b_r_mode_in_bounds )
109 {
110 vu16 *regsptr;
111 vu16 *regstmp1;
112
113 regsptr = &_spu_RXX[512 * _spu_core];
114 b_set_spucnt = (regsptr[205] >> 7) & 1;
115 if ( b_set_spucnt )
116 regsptr[205] &= ~0x80u;
117 regstmp1 = &_spu_RXX[20 * _spu_core];
118 regstmp1[946] = 0;
119 regstmp1[947] = 0;
120 _spu_rev_attr.depth.left = 0;
121 _spu_rev_attr.depth.right = 0;
122 }
123 else
124 {
125 if ( (mask & SPU_REV_DEPTHL) != 0 )
126 {
127 _spu_RXX[20 * _spu_core + 946] = attr->depth.left;
128 _spu_rev_attr.depth.left = attr->depth.left;
129 }
130 if ( (mask & SPU_REV_DEPTHR) != 0 )
131 {
132 _spu_RXX[20 * _spu_core + 947] = attr->depth.right;
133 _spu_rev_attr.depth.right = attr->depth.right;
134 }
135 }
136 if ( b_r_mode_in_bounds || b_mode_is_7_to_9_bit0x8 || b_mode_is_7_to_9_bit0x10 )
137 _spu_setReverbAttr(&entry);
138 if ( b_clear_reverb_work_area )
139 SpuClearReverbWorkArea(_spu_rev_attr.mode);
140 if ( b_r_mode_in_bounds )
141 {
142 _spu_FsetRXX(368, _spu_rev_offsetaddr, 1);
143 if ( b_set_spucnt )
144 _spu_RXX[512 * _spu_core + 205] |= 0x80u;
145 }
146 return 0;
147}