11#include "libspu2_internal.h"
16 int b_r_mode_in_bounds;
17 int b_mode_is_7_to_9_bit0x8;
19 int b_mode_is_7_to_9_bit0x10;
22 int b_clear_reverb_work_area;
25 b_r_mode_in_bounds = 0;
26 b_mode_is_7_to_9_bit0x8 = 0;
27 b_clear_reverb_work_area = 0;
29 b_mode_is_7_to_9_bit0x10 = 0;
33 if ( (mask & SPU_REV_MODE) != 0 )
38 if ( (mode & SPU_REV_MODE_CLEAR_WA) != 0 )
40 mode &= ~SPU_REV_MODE_CLEAR_WA;
41 b_clear_reverb_work_area = 1;
43 b_r_mode_in_bounds = 1;
44 if ( mode >= SPU_REV_MODE_MAX )
46 _spu_rev_attr.mode = mode;
47 _spu_rev_offsetaddr = SpuGetReverbEndAddr() - (8 * _spu_rev_workareasize[mode] - 2);
48 printf(
"_spu_rev_offsetaddr %x\n", _spu_rev_offsetaddr);
49 memcpy(&entry, &_spu_rev_param[_spu_rev_attr.mode],
sizeof(entry));
50 switch ( _spu_rev_attr.mode )
52 case SPU_REV_MODE_ECHO:
53 _spu_rev_attr.feedback = 127;
54 _spu_rev_attr.delay = 127;
56 case SPU_REV_MODE_DELAY:
57 _spu_rev_attr.feedback = 0;
58 _spu_rev_attr.delay = 127;
61 _spu_rev_attr.feedback = 0;
62 _spu_rev_attr.delay = 0;
67 ((mask & SPU_REV_DELAYTIME) != 0) && _spu_rev_attr.mode <= SPU_REV_MODE_DELAY
68 && _spu_rev_attr.mode >= SPU_REV_MODE_ECHO )
72 b_mode_is_7_to_9_bit0x8 = 1;
73 if ( !b_r_mode_in_bounds )
75 memcpy(&entry, &_spu_rev_param[_spu_rev_attr.mode],
sizeof(entry));
76 entry.flags = 0xc011c00;
78 _spu_rev_attr.delay = attr->delay;
79 entry.mLSAME = (s16)((_spu_rev_attr.delay & 0xFFFF) << 13) / 127 - entry.dAPF1;
80 delay_converted = (_spu_rev_attr.delay << 12) / 127;
81 entry.mRSAME = delay_converted - entry.dAPF2;
82 entry.dLSAME = entry.dRSAME + delay_converted;
83 entry.mLCOMB1 = entry.mRCOMB1 + delay_converted;
84 entry.mRAPF1 = entry.mRAPF2 + delay_converted;
85 entry.mLAPF1 = entry.mLAPF2 + delay_converted;
88 ((mask & SPU_REV_FEEDBACK) != 0) && _spu_rev_attr.mode <= SPU_REV_MODE_DELAY
89 && _spu_rev_attr.mode >= SPU_REV_MODE_ECHO )
91 b_mode_is_7_to_9_bit0x10 = 1;
92 if ( !b_r_mode_in_bounds )
94 if ( b_mode_is_7_to_9_bit0x8 )
96 flagstmp = entry.flags | 0x80;
100 memcpy(&entry, &_spu_rev_param[_spu_rev_attr.mode],
sizeof(entry));
103 entry.flags = flagstmp;
105 _spu_rev_attr.feedback = attr->feedback;
106 entry.vWALL = 33024 * _spu_rev_attr.feedback / 127;
108 if ( b_r_mode_in_bounds )
113 regsptr = &_spu_RXX[512 * _spu_core];
114 b_set_spucnt = (regsptr[205] >> 7) & 1;
116 regsptr[205] &= ~0x80u;
117 regstmp1 = &_spu_RXX[20 * _spu_core];
120 _spu_rev_attr.depth.left = 0;
121 _spu_rev_attr.depth.right = 0;
125 if ( (mask & SPU_REV_DEPTHL) != 0 )
127 _spu_RXX[20 * _spu_core + 946] = attr->depth.left;
128 _spu_rev_attr.depth.left = attr->depth.left;
130 if ( (mask & SPU_REV_DEPTHR) != 0 )
132 _spu_RXX[20 * _spu_core + 947] = attr->depth.right;
133 _spu_rev_attr.depth.right = attr->depth.right;
136 if ( b_r_mode_in_bounds || b_mode_is_7_to_9_bit0x8 || b_mode_is_7_to_9_bit0x10 )
137 _spu_setReverbAttr(&entry);
138 if ( b_clear_reverb_work_area )
139 SpuClearReverbWorkArea(_spu_rev_attr.mode);
140 if ( b_r_mode_in_bounds )
142 _spu_FsetRXX(368, _spu_rev_offsetaddr, 1);
144 _spu_RXX[512 * _spu_core + 205] |= 0x80u;