94 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
182 unsigned int y,
unsigned int Width,
unsigned int Height,
188 } enable_path3 ALIGNED(16) = {
189 {PS2SS_VIF1_MSKPATH3(0), PS2SS_VIF1_NOP, PS2SS_VIF1_NOP, PS2SS_VIF1_NOP}
192 u32 dma_chain[20*2] ALIGNED(16);
193 u32* p_dma32 = (u32*)&dma_chain;
194 u64 *p_dma64 = (u64*)(p_dma32 + 4);
201 if( Psm == PS2SS_GSPSMCT16 )
202 uQSize = ((Width*Height*2)/16);
203 else if( Psm == PS2SS_GSPSMCT24 )
204 uQSize = ((Width*Height*3)/16);
206 uQSize = (Width*Height*4)/16;
210 p_dma32[0] = PS2SS_VIF1_NOP;
211 p_dma32[1] = PS2SS_VIF1_MSKPATH3(0x8000);
212 p_dma32[2] = PS2SS_VIF1_FLUSHA;
213 p_dma32[3] = PS2SS_VIF1_DIRECT(6);
217 p_dma64[0] = PS2SS_GIFTAG(5, 1, 0, 0, 0, 1);
218 p_dma64[1] = PS2SS_GIF_AD;
220 p_dma64[2] = PS2SS_GSBITBLTBUF_SET(VramAdress, Width/64, Psm, 0, 0, Psm);
221 p_dma64[3] = PS2SS_GSBITBLTBUF;
223 p_dma64[4] = PS2SS_GSTRXPOS_SET(x, y, 0, 0, 0);
224 p_dma64[5] = PS2SS_GSTRXPOS;
226 p_dma64[6] = PS2SS_GSTRXREG_SET(Width, Height);
227 p_dma64[7] = PS2SS_GSTRXREG;
230 p_dma64[9] = PS2SS_GSFINISH;
232 p_dma64[10] = PS2SS_GSTRXDIR_SET(1);
233 p_dma64[11] = PS2SS_GSTRXDIR;
235 prev_imr = GsPutIMR(GsGetIMR() | 0x0200);
236 prev_chcr = *PS2SS_D1_CHCR;
238 if( (*PS2SS_D1_CHCR & 0x0100) != 0 )
243 *PS2SS_GS_CSR = PS2SS_CSR_FINISH;
250 *PS2SS_D1_MADR = (u32)p_dma32;
251 *PS2SS_D1_CHCR = 0x101;
253 asm __volatile__(
"sync.l\n");
257 while( *PS2SS_D1_CHCR & 0x0100 );
258 while( ( *PS2SS_GS_CSR & PS2SS_CSR_FINISH ) == 0 );
262 while( (*PS2SS_VIF1_STAT & (0x1f000000) ) );
266 *PS2SS_VIF1_STAT = PS2SS_VIF1_STAT_FDR;
267 *PS2SS_GS_BUSDIR = (u64)0x00000001;
271 *PS2SS_D1_QWC = uQSize;
272 *PS2SS_D1_MADR = (u32)pDest;
273 *PS2SS_D1_CHCR = 0x100;
275 asm __volatile__(
" sync.l\n");
279 while ( *PS2SS_D1_CHCR & 0x0100 );
280 *PS2SS_D1_CHCR = prev_chcr;
281 asm __volatile__(
" sync.l\n");
282 *PS2SS_VIF1_STAT = 0;
283 *PS2SS_GS_BUSDIR = (u64)0;
287 GsPutIMR( prev_imr );
288 *PS2SS_GS_CSR = PS2SS_CSR_FINISH;
293 *PS2SS_VIF1_FIFO = enable_path3.value;