11#include "irx_imports.h"
26IRX_ID(
"sio2man_logger", 3, 17);
28IRX_ID(
"sio2man", 3, 17);
41 int m_transfer_semaphore;
44 int m_sdk13x_totalflag;
45 sio2_mtap_change_slot_cb_t m_mtap_change_slot_cb;
46 sio2_mtap_get_slot_max_cb_t m_mtap_get_slot_max_cb;
47 sio2_mtap_get_slot_max2_cb_t m_mtap_get_slot_max2_cb;
48 sio2_mtap_update_slots_t m_mtap_update_slots_cb;
51#define EPRINTF(format, args...) printf("%s: " format, _irx_id.n, ##args)
56#define sio2_ctrl_set inl_sio2_ctrl_set
57#define sio2_ctrl_get inl_sio2_ctrl_get
58#define sio2_stat6c_get inl_sio2_stat6c_get
59#define sio2_portN_ctrl1_set inl_sio2_portN_ctrl1_set
60#define sio2_portN_ctrl2_set inl_sio2_portN_ctrl2_set
61#define sio2_regN_set inl_sio2_regN_set
62#define sio2_stat74_get inl_sio2_stat74_get
63#define sio2_data_out inl_sio2_data_out
64#define sio2_data_in inl_sio2_data_in
65#define sio2_stat_set inl_sio2_stat_set
66#define sio2_stat_get inl_sio2_stat_get
67#define sio2_set_ctrl_c inl_sio2_set_ctrl_c
68#define sio2_set_ctrl_1 inl_sio2_set_ctrl_1
69#define NANO_STATIC static inline
74NANO_STATIC
void sio2_ctrl_set(u32 val)
76 USE_IOP_MMIO_HWPORT();
78 iop_mmio_hwport->sio2.ctrl = val;
81NANO_STATIC u32 sio2_ctrl_get(
void)
83 USE_IOP_MMIO_HWPORT();
85 return iop_mmio_hwport->sio2.ctrl;
88NANO_STATIC u32 sio2_stat6c_get(
void)
90 USE_IOP_MMIO_HWPORT();
92 return iop_mmio_hwport->sio2.recv1;
95NANO_STATIC
void sio2_portN_ctrl1_set(
int N, u32 val)
97 USE_IOP_MMIO_HWPORT();
99 iop_mmio_hwport->sio2.send1_2_buf[N * 2] = val;
103u32 sio2_portN_ctrl1_get(
int N)
105 USE_IOP_MMIO_HWPORT();
107 return iop_mmio_hwport->sio2.send1_2_buf[N * 2];
111NANO_STATIC
void sio2_portN_ctrl2_set(
int N, u32 val)
113 USE_IOP_MMIO_HWPORT();
115 iop_mmio_hwport->sio2.send1_2_buf[(N * 2) + 1] = val;
119u32 sio2_portN_ctrl2_get(
int N)
121 USE_IOP_MMIO_HWPORT();
123 return iop_mmio_hwport->sio2.send1_2_buf[(N * 2) + 1];
127u32 sio2_stat70_get(
void)
129 USE_IOP_MMIO_HWPORT();
131 return iop_mmio_hwport->sio2.recv2;
134NANO_STATIC
void sio2_regN_set(
int N, u32 val)
136 USE_IOP_MMIO_HWPORT();
138 iop_mmio_hwport->sio2.send3_buf[N] = val;
142u32 sio2_regN_get(
int N)
144 USE_IOP_MMIO_HWPORT();
146 return iop_mmio_hwport->sio2.send3_buf[N];
150NANO_STATIC u32 sio2_stat74_get(
void)
152 USE_IOP_MMIO_HWPORT();
154 return iop_mmio_hwport->sio2.recv3;
158void sio2_unkn78_set(u32 val)
160 USE_IOP_MMIO_HWPORT();
162 iop_mmio_hwport->sio2.unk_78 = val;
167u32 sio2_unkn78_get(
void)
169 USE_IOP_MMIO_HWPORT();
171 return iop_mmio_hwport->sio2.unk_78;
176void sio2_unkn7c_set(u32 val)
178 USE_IOP_MMIO_HWPORT();
180 iop_mmio_hwport->sio2.unk_7c = val;
185u32 sio2_unkn7c_get(
void)
187 USE_IOP_MMIO_HWPORT();
189 return iop_mmio_hwport->sio2.unk_7c;
193NANO_STATIC
void sio2_data_out(u8 val)
195 USE_IOP_MMIO_HWPORT();
197 iop_mmio_hwport->sio2.out_fifo = val;
200NANO_STATIC u8 sio2_data_in(
void)
202 USE_IOP_MMIO_HWPORT();
204 return iop_mmio_hwport->sio2.in_fifo;
207NANO_STATIC
void sio2_stat_set(u32 val)
209 USE_IOP_MMIO_HWPORT();
211 iop_mmio_hwport->sio2.stat = val;
214NANO_STATIC u32 sio2_stat_get(
void)
216 USE_IOP_MMIO_HWPORT();
218 return iop_mmio_hwport->sio2.stat;
226 log_default(LOG_TRS);
229 for ( i = 0; i < 4; i += 1 )
231 sio2_portN_ctrl1_set(i, td->port_ctrl1[i]);
232 sio2_portN_ctrl2_set(i, td->port_ctrl2[i]);
236 log_portdata(td->port_ctrl1, td->port_ctrl2);
239 for ( i = 0; i < 16; i += 1 )
240 sio2_regN_set(i, td->regdata[i]);
243 log_regdata(td->regdata);
246 for ( i = 0; i < (int)td->in_size; i += 1 )
247 sio2_data_out(td->in[i]);
250 log_data(LOG_TRS_DATA, td->in, td->in_size);
252 if ( td->in_dma.addr )
254 sceSetSliceDMA(IOP_DMAC_SIO2in, td->in_dma.addr, td->in_dma.size, td->in_dma.count, DMAC_FROM_MEM);
255 sceStartDMA(IOP_DMAC_SIO2in);
257 log_dma(LOG_TRS_DMA_IN, &td->in_dma);
260 if ( td->out_dma.addr )
262 sceSetSliceDMA(IOP_DMAC_SIO2out, td->out_dma.addr, td->out_dma.size, td->out_dma.count, DMAC_TO_MEM);
263 sceStartDMA(IOP_DMAC_SIO2out);
265 log_dma(LOG_TRS_DMA_OUT, &td->out_dma);
275 log_default(LOG_TRR);
277 td->stat6c = sio2_stat6c_get();
278 td->stat70 = sio2_stat70_get();
279 td->stat74 = sio2_stat74_get();
281 log_stat(td->stat6c, td->stat70, td->stat74);
283 for ( i = 0; i < (int)td->out_size; i += 1 )
284 td->out[i] = sio2_data_in();
287 log_data(LOG_TRR_DATA, td->out, td->out_size);
293 sio2_stat_set(sio2_stat_get());
294 iSignalSema(arg->m_intr_sema);
298int _start(
int ac,
char **av)
306 if ( RegisterLibraryEntries(&_exp_sio2man) != 0 )
309 _exp_sio2man1.name[7] =
'\x00';
310 if ( RegisterLibraryEntries(&_exp_sio2man1) != 0 )
312 if ( g_sio2man_data.m_inited )
314 g_sio2man_data.m_inited = 1;
315 g_sio2man_data.m_sdk13x_curflag = 0;
316 g_sio2man_data.m_sdk13x_totalflag = 3;
319 sio2_mtap_change_slot_set(NULL);
320 sio2_mtap_get_slot_max_set(NULL);
321 sio2_mtap_get_slot_max2_set(NULL);
322 sio2_mtap_update_slots_set(NULL);
324 sio2_ctrl_set(0x3BC);
329 sceSetDMAPriority(IOP_DMAC_SIO2in, 3);
330 sceSetDMAPriority(IOP_DMAC_SIO2out, 3);
331 sceEnableDMAChannel(IOP_DMAC_SIO2in);
332 sceEnableDMAChannel(IOP_DMAC_SIO2out);
334 semaparam.option = 0;
335 semaparam.initial = 1;
337 g_sio2man_data.m_transfer_semaphore = CreateSema(&semaparam);
339 semaparam.option = 0;
340 semaparam.initial = 0;
342 g_sio2man_data.m_intr_sema = CreateSema(&semaparam);
344 EPRINTF(
"Logging started.\n");
354 if ( !g_sio2man_data.m_inited )
360 g_sio2man_data.m_inited = 0;
366 sceDisableDMAChannel(IOP_DMAC_SIO2in);
367 sceDisableDMAChannel(IOP_DMAC_SIO2out);
368 DeleteSema(g_sio2man_data.m_intr_sema);
369 DeleteSema(g_sio2man_data.m_transfer_semaphore);
373void sio2_set_intr_handler(
int (*handler)(
void *),
void *userdata)
381 IOP_IRQ_SIO2, 1, handler ? handler : (
int (*)(
void *))sio2_intr_handler, handler ? userdata : &g_sio2man_data);
387NANO_STATIC
void sio2_set_ctrl_c()
390 sio2_ctrl_set(sio2_ctrl_get() | 0xC);
393NANO_STATIC
void sio2_set_ctrl_1()
396 sio2_ctrl_set(sio2_ctrl_get() | 1);
399void sio2_wait_for_intr()
401 WaitSema(g_sio2man_data.m_intr_sema);
412 sio2_wait_for_intr();
414 if ( g_sio2man_data.m_sdk13x_curflag )
415 sio2_transfer_reset();
422void sio2_pad_transfer_init(
void)
427 WaitSema(g_sio2man_data.m_transfer_semaphore);
429 log_default(LOG_PAD_READY);
431 g_sio2man_data.m_sdk13x_curflag = 0;
434void sio2_pad_transfer_init_possiblysdk13x(
void)
436 sio2_pad_transfer_init();
437 g_sio2man_data.m_sdk13x_curflag |= g_sio2man_data.m_sdk13x_totalflag & 1;
440void sio2_mc_transfer_init_possiblysdk13x(
void)
442 sio2_pad_transfer_init();
443 g_sio2man_data.m_sdk13x_curflag |= g_sio2man_data.m_sdk13x_totalflag & 2;
446void sio2_transfer_reset(
void)
448 g_sio2man_data.m_sdk13x_curflag = 0;
449 SignalSema(g_sio2man_data.m_transfer_semaphore);
451 log_default(LOG_RESET);
455static int sio2_mtap_change_slot_default(s32 *arg)
461 for ( i = 0; i < 4; i += 1 )
463 arg[i + 4] = ((arg[i] + 1) < 2);
469static int sio2_mtap_get_slot_max_default(
int port)
474static void sio2_mtap_update_slots_default(
void) {}
476void sio2_mtap_change_slot_set(sio2_mtap_change_slot_cb_t cb)
479 g_sio2man_data.m_mtap_change_slot_cb = cb ? cb : sio2_mtap_change_slot_default;
482void sio2_mtap_get_slot_max_set(sio2_mtap_get_slot_max_cb_t cb)
485 g_sio2man_data.m_mtap_get_slot_max_cb = cb ? cb : sio2_mtap_get_slot_max_default;
488void sio2_mtap_get_slot_max2_set(sio2_mtap_get_slot_max2_cb_t cb)
491 g_sio2man_data.m_mtap_get_slot_max2_cb = cb ? cb : sio2_mtap_get_slot_max_default;
494void sio2_mtap_update_slots_set(sio2_mtap_update_slots_t cb)
497 g_sio2man_data.m_mtap_update_slots_cb = cb ? cb : sio2_mtap_update_slots_default;
500int sio2_mtap_change_slot(s32 *arg)
502 g_sio2man_data.m_sdk13x_totalflag &= ~g_sio2man_data.m_sdk13x_curflag;
504 return g_sio2man_data.m_mtap_change_slot_cb(arg);
507int sio2_mtap_get_slot_max(
int port)
510 return g_sio2man_data.m_mtap_get_slot_max_cb(port);
513int sio2_mtap_get_slot_max2(
int port)
516 return g_sio2man_data.m_mtap_get_slot_max2_cb(port);
519void sio2_mtap_update_slots(
void)
522 g_sio2man_data.m_mtap_update_slots_cb();
int CpuResumeIntr(int state)
int RegisterIntrHandler(int irq, int mode, int(*handler)(void *), void *arg)
int ReleaseIntrHandler(int irq)
int DisableIntr(int irq, int *res)
int CpuSuspendIntr(int *state)