68 27:24 DMAT DMA timing: /SRD /SWR active.low period: 0-14 [cycles+1]. The inactive period is always 1cycle.
69 0=1cycle, 1=2cycles, ..., 14=15cy
70 15(0xF)= '0.5cycles' Each word still remains on the bus for 1cy, but there are no inactive pauses between the words.
71 - 'fastest' DMA mode: /SRD/SWR is kept active low over the whole transfer and the SSCLK clocks the data words.
72 On some devices (PS2 mode only?) the /SRD active low period cannot be 1 cycle, thus with DMAT = 0 or 1, the resulting period is 2cy.
73 It is unknown if this is caused by some setting. The /SWR period is unaffected.
74 28 ADER r/o Address error flag (when =1). When the an address error within the memory range of this channel occurs this bit becomes set.
75 Writing 1 clears it. Unknown what Address Error means. This doesn't become set by unaligned access.
76 It might be for the DMAC accessing RAM past its end when doing DMA through this SSBUSC channel, but it doesn't activate on that either.
77 29 DMAF DMA select timing source flag: 0= use PIO timing / 1= use DMA timing bit-field 28:24 for DMA.
78 30 WDMA Wide DMA mode. When = 1 this overrides the Access Type (8/16 bit) setting, and causes 32 bits to be transferred in one go.
79 The low 16bits are mapped to the SD15:SD0 data lines, and the high 16bits - to the low address lines SA15:SA0, which become inputs,
80 if the transfer is done 'to RAM'.
81 This is why most devices get all the low 16 address bits, even though their address space is much smaller than 64kbyte.
82 The SPU2 doesn't get all 16 low address lines, so this is disabled for it, while it is enabled for the CDVD and Dev9M, Dev9I.
83 31 WAIT /WAIT signal. When = 1 enables the IOP waiting on the /WAIT (input to IOP) signal, when accessing the range of the given device.
84 Slow devices can make the IOP wait (indefinitely) before transferring data, by asserting the /WAIT line low while a PIO access is being done
85 (after the device detected assertion of /CS and decoded the address).
86 On read, once /WAIT is deasserted, IOP loads the data (it was made to wait for) from the device/bus (on read) and continues execution.
87 On write the write operation completes even if /WAIT is asserted low and the IOP can continue executing. This is true for any device.
88 However if /WAIT is kept asserted low and another write (or a read) access is done (to any device - even such with /WAIT hardwired to disabled state),
89 then the IOP will stall before (or after?) transferring any data, until /WAIT is deasserted.
90 This can be used as a hack to use /WAIT even of devices that have it disabled (like the BOOT ROM for example):
91 write a device that has it enabled (while /WAIT is low) then access (r/w) the BOOT ROM and the IOP will stall until /WAIT is deasserted.
92 /WAIT should be driven most likely by OC/OD drivers (or a tri-state output enabled on /CS). The output of the Dev9C seems to be just such.
93
94 There are two main modes of transfer: PIO and DMA.
95 The timing parameters of the PIO mode can be set in detail, while for the DMA mode a symmetric clock is assumed only with period configurable.
96 PIO timing configuration can be used for DMA transfers too.
97
98 For DMA on read (->IOP) both for 0 and 1 DMA periods 1 cycle is added, which results in 2 cycle transfer - reason unknown.
99 On write, 0->1cycle, 1->2cycles (reason unknown).
100
101 Besides the /SRD /SWR active.low periods that can be set individually for each channel,
102 the following parameters exist, that can only be enabled for the individual channels,
103 but the value is common for all. Their values are set by the Common Delay register.
114 Recovery period: Elongates with commonDelay.3:0 cycles the period after the data bus is released by the IOP (write) (after the added hold period, if any)
115 or after /SRD goes inact.high, to the next active /SRD/SWR pulse or /CS going inactive transition,
116 to give the device more time to release the bus on read or give more bus turnaround time to the next access on write.
117
118 Hold period: The period after /SWR goes inact.high when the data bus keeps its data valid, necessary for signal propagation and correct latching.
119 The /SWR active.low inter-pulse period will be elongated with commonDelay.7:4 cycles in which after /SWR goes inactive.high the data output from the IOP would still be kept valid.
120 This setting has no effect on /SRD read timing.
121
122 Floating period: Elongate the /CS (active low) and the inter-/SRD pulses periods after /SRD goes inactive to give the device more time to leave the bus
123 floating after driving it (for slow devices that release the bus slowly).
124 Give the device commonDelay.11:8 cycles more after /SRD goes inactive to the next /SRD pulse or the end of the cycle (/CS -> inact.high),
125 to leave the bus floating. When set to 0, the period /SRD inact.high-going edge to /CS inact.high -going edge is 1/2 cycle and is 1cy between /SRD pulses act.low pulses.
126 This setting has no effect on /SWR write timing.
127
128 Pre-Strobe period: Delay from the start of data output (and /CS going active.low) to the active.low -going edge of /SRD or /SWR:
129 Shifts the active-going edge of /SWR the commonDelay.15:12 cycles later than it would usually come,
130 so data can be read on the active-going falling edge.
131 If the active period of the act.low pulse is less than this strobe delay, then the inactive periods between pulses are elongated to account for that.
132 The active pulse is shrunk to a minimum of 1cy in this case. /CS act.low-going edge to /SRD or /SWR act-low going edge is of this number of cycles (otherwise = 0).
133 While delayReg./SRD/SWR_act.low_period <= strobePeriod, no change in the total period is done.
134 Pulse active.low period = max((delayReg.act.low_period - strobePer), 1). - at least 1 cy. This has the same effect on both /SRD and /SWR. */
1.8.17