PS2SDK
PS2 Homebrew Libraries
xatapi.c
1 /*
2 # _____ ___ ____ ___ ____
3 # ____| | ____| | | |____|
4 # | ___| |____ ___| ____| | \ PS2DEV Open Source Project.
5 #-----------------------------------------------------------------------
6 # Copyright ps2dev - http://www.ps2dev.org
7 # Licenced under Academic Free License version 2.0
8 # Review ps2sdk README & LICENSE files for further details.
9 */
10 
11 #include "irx_imports.h"
12 #include <errno.h>
13 #include <kerr.h>
14 #include <xatapi.h>
15 
16 #ifdef _IOP
17 IRX_ID("cdvd_xatapi_driver", 2, 3);
18 #endif
19 // Based off of DESR / PSX DVR system software version 2.11.
20 
21 typedef struct _ata_cmd_state
22 {
23  s32 type;
24  union
25  {
26  void *buf;
27  u8 *buf8;
28  u16 *buf16;
29  };
30  u32 blkcount;
31  s32 dir;
32  s32 type_atapi;
33  void *buf_atapi;
34  u32 blkcount_atapi;
35  u32 blksize_atapi;
36  s32 dir_atapi;
37 } ata_cmd_state_t;
38 
39 typedef struct _ata_devinfo
40 {
41  s32 exists;
42  s32 has_packet;
43  u32 total_sectors;
44  u32 security_status;
45  u32 lba48;
46 } ata_devinfo_t;
47 
48 struct dev5_speed_regs_
49 {
50  vu16 unv00;
51  vu16 r_spd_rev_1;
52  vu16 r_spd_rev_3;
53  vu16 unv06;
54  vu16 unv08;
55  vu16 unv0a;
56  vu16 unv0c;
57  vu16 r_spd_rev_8;
58  vu16 unv10;
59  vu16 unv12;
60  vu16 unv14;
61  vu16 unv16;
62  vu16 unv18;
63  vu16 unv1a;
64  vu16 unv1c;
65  vu16 unv1e;
66  vu16 unv20;
67  vu16 unv22;
68  vu16 r_spd_dma_ctrl;
69  vu16 unv26;
70  vu16 r_spd_intr_stat;
71  vu16 r_spd_intr_mask;
72  vu16 unv2c;
73  vu16 r_spd_pio_data;
74  vu16 unv30;
75  vu16 r_spd_xfr_ctrl;
76  vu16 unv34;
77  vu16 m_spd_unk36;
78  vu16 r_spd_dbuf_stat;
79  vu16 unv3a;
80  vu16 unv3c;
81  vu16 unv3e;
82  vu16 r_spd_ata_data;
83  vu16 r_spd_ata_error;
84  vu16 r_spd_ata_nsector;
85  vu16 r_spd_ata_sector;
86  vu16 r_spd_ata_lcyl;
87  vu16 r_spd_ata_hcyl;
88  vu16 r_spd_ata_select;
89  vu16 r_spd_ata_status;
90  vu16 unv50;
91  vu16 unv52;
92  vu16 unv54;
93  vu16 unv56;
94  vu16 unv58;
95  vu16 unv5a;
96  vu16 r_spd_ata_control;
97  vu16 unv5e;
98  vu16 unv60;
99  vu16 unv62;
100  vu16 r_spd_if_ctrl;
101  vu16 unv66;
102  vu16 unv68;
103  vu16 unv6a;
104  vu16 unv6c;
105  vu16 unv6e;
106  vu16 r_spd_pio_mode;
107  vu16 r_spd_mwdma_mode;
108  vu16 r_spd_udma_mode;
109 };
110 // cppcheck-suppress-macro constVariablePointer
111 #define USE_DEV5_SPEED_REGS() struct dev5_speed_regs_ *const dev5_speed_regs = (void *)0xBF410000
112 
113 struct dev5_fpga_regs_
114 {
115  vu16 r_fpga_layer1;
116  vu16 r_fpga_xfrdir;
117  vu16 r_fpga_xfren;
118  vu16 r_fpga_layer2;
119  vu16 r_fpga_sl3bufe;
120  vu16 r_fpga_sl3bufd;
121  vu16 unv0c;
122  vu16 unv0e;
123  vu16 unv10;
124  vu16 r_fpga_exbufd;
125  vu16 r_fpga_exbufe;
126  vu16 unv16;
127  vu16 unv18;
128  vu16 unv1a;
129  vu16 unv1c;
130  vu16 unv1e;
131  vu16 unv20;
132  vu16 unv22;
133  vu16 unv24;
134  vu16 unv26;
135  vu16 unv28;
136  vu16 unv2a;
137  vu16 unv2c;
138  vu16 unv2e;
139  vu16 r_fpga_unk30;
140  vu16 r_fpga_spckmode;
141  vu16 r_fpga_spckcnt;
142  vu16 unvpad[2013];
143  vu16 r_fpga_revision;
144 };
145 // cppcheck-suppress-macro constVariablePointer
146 #define USE_DEV5_FPGA_REGS() struct dev5_fpga_regs_ *const dev5_fpga_regs = (void *)0xBF414000
147 
148 static int xatapi_dev_devctl(
149  const iop_file_t *f, const char *name, int cmd, void *args, unsigned int arglen, void *buf, unsigned int buflen);
150 static void speed_init(void);
151 static void speed_device_init(void);
152 static void do_hex_dump(void *ptr, int len);
153 static void ata_pio_mode(int mode);
154 static void ata_multiword_dma_mode(int mode);
155 static void ata_ultra_dma_mode(int mode);
156 static void AtaEjectIntrHandle(void);
157 static int sceCdAtapiExecCmd_local(s16 n, void *buf, int nsec, int secsize, void *pkt, unsigned int pkt_len, int proto);
158 static int sceCdAtapiExecCmd(s16 n, void *buf, int nsec, int secsize, void *pkt, int pkt_len, int proto);
159 static void DmaRun_spck(char *buf, unsigned int secsize);
160 static int sceCdAtapiWaitResult_local(void);
161 static void atapi_device_set_transfer_mode_outer(int device);
162 static void ata_device_set_transfer_mode_outer(int device);
163 static void sceAtapiInit(int device);
164 static void sceAtInterInit(void);
165 static int create_event_flags(void);
166 static void FpgaLayer1On(void);
167 static void FpgaLayer1Off(void);
168 static void FpgaLayer2Off(void);
169 static void FpgaXfrenOn(void);
170 static void FpgaXfrenOff(void);
171 static void FpgaSpckmodeOn(void);
172 static void FpgaSpckmodeOff(void);
173 static void FpgaXfdir(int dir);
174 static int FpgaGetRevision(void);
175 static int do_fpga_check_spckcnt(void);
176 static void FpgaCheckWriteBuffer(void);
177 static void FpgaCheckWriteBuffer2(void);
178 static void FpgaClearBuffer(void);
179 static int Mpeg2CheckPadding(char *buf, unsigned int bufsize, int *retptr, int *pesscramblingpackptr);
180 static int Mpeg2CheckScramble(char *buf, unsigned int bufsize);
181 
182 extern struct irx_export_table _exp_xatapi;
183 // Unofficial: move to bss
184 static int g_devctl_retonly_unset;
185 static vu16 *const g_dev9_reg_1460 = (void *)0xBF801460;
186 static vu16 *const g_dev9_reg_power = (void *)0xBF80146C;
187 // Unofficial: move to bss
188 static int (*p_dev5_intr_cb)(int flag);
189 
190 // cppcheck-suppress unusedFunction
191 IOMANX_RETURN_VALUE_IMPL(0);
192 // unofficial: don't print on nulldev0 call
193 IOMANX_RETURN_VALUE_IMPL(EIO);
194 
195 static iop_device_ops_t ata_ioman_devops = {
196  IOMANX_RETURN_VALUE(0), IOMANX_RETURN_VALUE(0), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO),
197  IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO),
198  IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO),
199  IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO),
200  IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO),
201  IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE_S64(EIO), (void *)&xatapi_dev_devctl,
202  IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO),
203 };
204 static iop_device_t ata_ioman_device = {"xatapi", IOP_DT_FS | IOP_DT_FSEXT, 1, "CD-ROM_ATAPI", &ata_ioman_devops};
205 // Unofficial: move to bss
206 static int g_reset_scrambling_pack;
207 // Unofficial: move to bss
208 static int g_pes_scrambling_control_pack;
209 // Unofficial: move to bss
210 static int g_dma_mode_value;
211 // Unofficial: move to bss
212 static int g_dma_speed_value;
213 // Unofficial: move to bss
214 static int g_should_wait_for_dma_flag;
215 // Unofficial: move to bss
216 static int g_is_wait_busy;
217 // Unofficial: move to bss
218 static int g_verbose_level;
219 // Unofficial: move to bss
220 static int g_ata_devinfo_init;
221 static int g_bf40200a_is_set_ptr;
222 static u32 *g_cd_sc_ffffffd9_ptr;
223 static int g_is_in_read_info;
224 static int g_io_event_flag;
225 static int g_adma_evfid;
226 static int g_acmd_evfid;
227 static int g_dma_lock_sema;
228 static void (*g_dev5_intr_cbs[16])(int flag);
229 static void (*g_dev5_predma_cbs[4])(u32 bcr_in, int dir);
230 static void (*g_dev5_postdma_cbs[4])(u32 bcr_in, int dir);
231 static int g_atapi_event_flag;
232 static ata_devinfo_t atad_devinfo[2];
233 static ata_cmd_state_t atad_cmd_state;
234 static int ata_param[128];
235 static int g_atapi_xfer_buf[130];
236 
237 static int do_atapi_cmd_inquiry_12h(s16 dev_nr)
238 {
239  int i;
240  int retres;
241  char pkt[12];
242  char outbuf[56];
243 
244  retres = 1;
245  for ( i = 0; retres && i < 16; i += 1 )
246  {
247  memset(pkt, 0, sizeof(pkt));
248  pkt[0] = 0x12;
249  pkt[4] = sizeof(outbuf);
250  retres = sceCdAtapiExecCmd_local(dev_nr, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2);
251  if ( retres )
252  continue;
253  retres = sceCdAtapiWaitResult_local();
254  if ( retres )
255  {
256  VERBOSE_KPRINTF(1, "Atapi Drive ATAPI_CMD_READ_EXT_INFO NG\n");
257  DelayThread(10000);
258  }
259  }
260  if ( retres )
261  return retres;
262  do_hex_dump(outbuf, sizeof(outbuf));
263  return strncmp(&outbuf[32], "BOOT", 4) ? 1 : 0;
264 }
265 
266 static int do_atapi_request_test_unit_ready(s16 dev_nr, int *errptr, int *ctrlptr)
267 {
268  int retres;
269  char pkt[12];
270 
271  *errptr = 0;
272  *ctrlptr = 0;
273  memset(pkt, 0, sizeof(pkt));
274  pkt[0] = 0;
275  retres = xatapi_7_sceCdAtapiExecCmd(dev_nr, 0, 0, 0, pkt, sizeof(pkt), 1);
276  if ( retres )
277  return retres;
278  retres = xatapi_8_sceCdAtapiWaitResult();
279  *errptr = (u8)xatapi_11_sceAtaGetError();
280  *ctrlptr = (u8)xatapi_12_get_ata_control();
281  return retres;
282 }
283 
284 static int atapi_req_sense_get(s16 dev_nr, int *retptr)
285 {
286  int result;
287  char pkt[12];
288  char outbuf[18];
289 
290  *retptr = 0;
291  memset(pkt, 0, sizeof(pkt));
292  pkt[0] = 3;
293  pkt[4] = sizeof(outbuf);
294  result = xatapi_7_sceCdAtapiExecCmd(dev_nr, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2);
295  if ( result )
296  return result;
297  result = xatapi_8_sceCdAtapiWaitResult();
298  if ( result )
299  return result;
300  *retptr = ((outbuf[2] & 0xF) << 16) | ((u8)outbuf[12] << 8) | (u8)outbuf[13];
301  return 0;
302 }
303 
304 #ifdef UNUSED_FUNC
305 static int atapi_exec_cmd_request_sense_03h_unused(s16 dev_nr, int *retptr)
306 {
307  int result;
308  char pkt[12];
309  char outbuf[18];
310 
311  *retptr = 0;
312  memset(pkt, 0, sizeof(pkt));
313  pkt[0] = 3;
314  pkt[4] = sizeof(outbuf);
315  result = sceCdAtapiExecCmd_local(dev_nr, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2);
316  if ( result )
317  return result;
318  result = sceCdAtapiWaitResult_local();
319  if ( result )
320  return result;
321  *retptr = ((outbuf[2] & 0xF) << 16) | ((u8)outbuf[12] << 8) | (u8)outbuf[13];
322  return 0;
323 }
324 #endif
325 
326 #ifdef UNUSED_FUNC
327 static int do_start_stop_unit_1bh_unused(void)
328 {
329  int i;
330  int retres;
331  char pkt[12];
332 
333  retres = 1;
334  for ( i = 0; i < 16 && retres && retres != -550; i += 1 )
335  {
336  memset(pkt, 0, sizeof(pkt));
337  pkt[0] = 0x1B;
338  pkt[4] = 2;
339  pkt[5] = 0;
340  retres = sceCdAtapiExecCmd_local(0, 0, 0, 0, pkt, sizeof(pkt), 1);
341  if ( retres )
342  continue;
343  retres = sceCdAtapiWaitResult_local();
344  if ( retres )
345  {
346  VERBOSE_KPRINTF(1, "Atapi Drive EJECT NG\n");
347  DelayThread(10000);
348  continue;
349  }
350  VERBOSE_KPRINTF(1, "Atapi Drive EJECT OK\n");
351  }
352  if ( !retres )
353  {
354  retres = 1;
355  for ( i = 0; i < 16 && retres && retres != -550; i += 1 )
356  {
357  memset(pkt, 0, sizeof(pkt));
358  pkt[0] = 0x1B;
359  pkt[4] = 3;
360  pkt[5] = 0;
361  retres = sceCdAtapiExecCmd_local(0, 0, 0, 0, pkt, sizeof(pkt), 1);
362  if ( retres )
363  continue;
364  retres = sceCdAtapiWaitResult_local();
365  if ( retres )
366  {
367  VERBOSE_KPRINTF(1, "Atapi Drive Spindle Start NG %d\n", i);
368  DelayThread(10000);
369  continue;
370  }
371  VERBOSE_KPRINTF(1, "Atapi Drive Spindle Start OK\n");
372  }
373  }
374  VERBOSE_KPRINTF(1, " PS2 Eject On Atapi Unit Dummy Eject Ret %d\n", retres);
375  return retres;
376 }
377 #endif
378 
379 static int chgsys_callback_cb(int *mediaptr, int want_atapi)
380 {
381  int i;
382  int tryres1;
383  int retres;
384  char pkt[12];
385  char outbuf1[6];
386 
387  *mediaptr = 4;
388  if ( want_atapi )
389  {
390  VERBOSE_KPRINTF(1, "Ps2 Drive Spindle -> Atapi \n");
391  retres = 1;
392  for ( i = 0; i < 10 && retres && retres != -550; i += 1 )
393  {
394  memset(pkt, 0, sizeof(pkt));
395  pkt[0] = 0x1B;
396  pkt[4] = 3;
397  pkt[5] = 0;
398  retres = sceCdAtapiExecCmd(0, 0, 0, 0, pkt, sizeof(pkt), 1);
399  if ( retres )
400  continue;
401  retres = sceCdAtapiWaitResult_local();
402  if ( retres )
403  {
404  VERBOSE_KPRINTF(1, "Atapi Drive Spindle Start NG %d\n", i);
405  DelayThread(10000);
406  continue;
407  }
408  VERBOSE_KPRINTF(1, "Atapi Drive Spindle Start OK\n");
409  }
410  return retres;
411  }
412  VERBOSE_KPRINTF(1, "Atapi Drive Spindle -> Ps2\n");
413  tryres1 = 1;
414  for ( i = 0; i < 16 && tryres1 && tryres1 != -550; i += 1 )
415  {
416  memset(pkt, 0, sizeof(pkt));
417  pkt[0] = 0xF6;
418  pkt[2] = 0xA0;
419  pkt[8] = 6;
420  tryres1 = sceCdAtapiExecCmd_local(0, outbuf1, 1, sizeof(outbuf1), pkt, sizeof(pkt), 2);
421  if ( tryres1 )
422  continue;
423  tryres1 = sceCdAtapiWaitResult_local();
424  if ( tryres1 )
425  {
426  VERBOSE_KPRINTF(1, "Atapi Drive ATAPI_CMD_READ_EXT_INFO NG\n");
427  DelayThread(10000);
428  }
429  }
430  if ( !tryres1 )
431  {
432  int maskchk;
433 
434  maskchk = (((u8)outbuf1[5] >> 1) ^ 1) & 1;
435  if ( (outbuf1[3] & 0x10) )
436  {
437  char outbuf[8];
438 
439  VERBOSE_KPRINTF(1, "Atapi Drive Media found.\n");
440  memset(pkt, 0, sizeof(pkt));
441  pkt[0] = 0xF6;
442  pkt[2] = 0xA2;
443  pkt[8] = sizeof(outbuf);
444  if (
445  !sceCdAtapiExecCmd_local(0, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2) && !sceCdAtapiWaitResult_local() )
446  {
447  VERBOSE_KPRINTF(1, "Atapi Drive Media DVD:%d.\n", outbuf[5] & 0x20);
448  *mediaptr = (outbuf[5] & 0x20) ? 3 : 2;
449  }
450  }
451  else
452  {
453  VERBOSE_KPRINTF(1, "Atapi Drive No Media or Now checking.\n");
454  VERBOSE_KPRINTF(1, "Atapi Drive No Media or No SpinUp.\n");
455  *mediaptr = 4;
456  }
457  if ( maskchk )
458  {
459  VERBOSE_KPRINTF(1, "Atapi Drive Spin Up.\n");
460  retres = 1;
461  for ( i = 0; i < 16 && retres && retres != -550; i += 1 )
462  {
463  memset(pkt, 0, sizeof(pkt));
464  pkt[0] = 0x1B;
465  pkt[5] = 0;
466  retres = sceCdAtapiExecCmd(0, 0, 0, 0, pkt, sizeof(pkt), 1);
467  if ( retres )
468  continue;
469  retres = sceCdAtapiWaitResult_local();
470  if ( retres )
471  {
472  VERBOSE_KPRINTF(1, "Atapi Drive Spindle Stop NG\n");
473  DelayThread(10000);
474  continue;
475  }
476  VERBOSE_KPRINTF(1, "Atapi Drive Spindle Stop OK\n");
477  }
478  return retres;
479  }
480  VERBOSE_KPRINTF(1, "Atapi Drive Not Spin Up.\n");
481  retres = 1;
482  for ( i = 0; i < 16 && retres && retres != -550; i += 1 )
483  {
484  memset(pkt, 0, sizeof(pkt));
485  pkt[0] = 0x1B;
486  pkt[4] = 2;
487  pkt[5] = 0;
488  retres = sceCdAtapiExecCmd(0, 0, 0, 0, pkt, sizeof(pkt), 1);
489  if ( retres )
490  continue;
491  retres = sceCdAtapiWaitResult_local();
492  if ( retres )
493  {
494  VERBOSE_KPRINTF(1, "Atapi Drive EJECT NG\n");
495  DelayThread(10000);
496  continue;
497  }
498  VERBOSE_KPRINTF(1, "Atapi Drive EJECT OK\n");
499  *mediaptr = 256;
500  }
501  return retres;
502  }
503  return tryres1;
504 }
505 
506 static int sceCdAtapi_SC(void)
507 {
508  int i;
509  int retres;
510  char pkt[12];
511 
512  memset(pkt, 0, sizeof(pkt));
513  retres = 1;
514  pkt[0] = 0xF9;
515  pkt[2] = 0xB1;
516  pkt[8] = 0;
517  for ( i = 0; i < 10 && retres; i += 1 )
518  {
519  retres = sceCdAtapiExecCmd_local(0, 0, 0, 0, pkt, sizeof(pkt), 1);
520  if ( retres || (retres = sceCdAtapiWaitResult_local()) )
521  DelayThread(10000);
522  }
523  if ( retres )
524  {
525  VERBOSE_KPRINTF(1, "sceCdAtapi SC fail\n");
526  return retres;
527  }
528  *g_cd_sc_ffffffd9_ptr = 0;
529  VERBOSE_KPRINTF(1, "sceCdAtapi SC OK\n");
530  return 0;
531 }
532 
533 int xatapi_15_exec_f6_f9_scsi(void)
534 {
535  int i;
536  int retres1;
537  int retres2;
538  char pkt[12];
539  char outbuf[6];
540 
541  memset(pkt, 0, sizeof(pkt));
542  retres1 = 1;
543  pkt[0] = 0xF6;
544  pkt[2] = 0xB1;
545  pkt[8] = 6;
546  for ( i = 0; i < 4 && retres1; i += 1 )
547  {
548  retres1 = sceCdAtapiExecCmd_local(0, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2);
549  if ( retres1 || (retres1 = sceCdAtapiWaitResult_local()) )
550  DelayThread(10000);
551  }
552  if ( retres1 && !(outbuf[4] & 0x80) )
553  return retres1;
554  memset(pkt, 0, sizeof(pkt));
555  retres2 = 1;
556  pkt[0] = 0xF9;
557  pkt[2] = 0xB2;
558  pkt[8] = 0;
559  for ( i = 0; i < 10 && retres2; i += 1 )
560  {
561  retres2 = sceCdAtapiExecCmd_local(0, 0, 0, 0, pkt, sizeof(pkt), 1);
562  if ( !retres2 )
563  {
564  retres2 = sceCdAtapiWaitResult_local();
565  if ( !retres2 )
566  continue;
567  }
568  DelayThread(10000);
569  }
570  return retres2;
571 }
572 
573 static int sceCdAtapi_BC(void)
574 {
575  int i;
576  int retres1;
577  int retres4;
578  char pkt[12];
579  iop_event_info_t efinfo;
580  u32 waresontmp;
581  u32 efbits;
582  char outbuf1[6];
583  {
584  memset(pkt, 0, sizeof(pkt));
585  retres1 = 1;
586  pkt[0] = 0xF6;
587  pkt[2] = 0xB1;
588  pkt[8] = sizeof(outbuf1);
589  for ( i = 0; i < 10 && retres1; i += 1 )
590  {
591  retres1 = sceCdAtapiExecCmd_local(0, outbuf1, 1, sizeof(outbuf1), pkt, sizeof(pkt), 2);
592  if ( retres1 || (retres1 = sceCdAtapiWaitResult_local()) )
593  DelayThread(10000);
594  }
595  }
596  if ( !retres1 || (outbuf1[4] & 0x80) )
597  {
598  int retres2;
599 
600  memset(pkt, 0, sizeof(pkt));
601  retres2 = 1;
602  pkt[0] = 0xF9;
603  pkt[2] = 0xB2;
604  pkt[8] = 0;
605  for ( i = 0; i < 10 && retres2; i += 1 )
606  {
607  retres2 = sceCdAtapiExecCmd_local(0, 0, 0, 0, pkt, sizeof(pkt), 1);
608  if ( !retres2 )
609  {
610  retres2 = sceCdAtapiWaitResult_local();
611  if ( !retres2 )
612  continue;
613  }
614  DelayThread(10000);
615  }
616  }
617  {
618  int retres3;
619  char outbuf[6];
620 
621  memset(pkt, 0, sizeof(pkt));
622  retres3 = 1;
623  pkt[0] = 0xF6;
624  pkt[2] = 0xB1;
625  pkt[8] = sizeof(outbuf);
626  for ( i = 0; i < 10 && retres3; i += 1 )
627  {
628  retres3 = sceCdAtapiExecCmd_local(0, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2);
629  if ( retres3 || (retres3 = sceCdAtapiWaitResult_local()) )
630  DelayThread(10000);
631  }
632  if ( !retres3 && (outbuf[4] & 0x81) )
633  {
634  *g_cd_sc_ffffffd9_ptr = 1;
635  return 1;
636  }
637  }
638  {
639  char outbuf[16];
640 
641  memset(pkt, 0, sizeof(pkt));
642  retres4 = 1;
643  pkt[0] = 0xF6;
644  pkt[2] = 0xB0;
645  pkt[8] = sizeof(outbuf);
646  for ( i = 0; i < 10 && retres4; i += 1 )
647  {
648  retres4 = sceCdAtapiExecCmd_local(0, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2);
649  if ( retres4 || (retres4 = sceCdAtapiWaitResult_local()) )
650  DelayThread(10000);
651  }
652  if ( retres4 )
653  {
654  VERBOSE_KPRINTF(1, "sceCdAtapi BC 0 fail\n");
655  }
656  else
657  {
658  int flg;
659 
660  if ( g_should_wait_for_dma_flag && !ReferEventFlagStatus(g_adma_evfid, &efinfo) && !efinfo.currBits )
661  SetEventFlag(g_adma_evfid, 1);
662  SetEventFlag(g_acmd_evfid, 1);
663  retres4 = 0;
664  for ( i = 0; i < 100 && !retres4; i += 1 )
665  {
666  retres4 = cdvdman_167_atapi2dragon((u8 *)outbuf, &waresontmp);
667  if ( !retres4 || waresontmp )
668  DelayThread(10000);
669  }
670  flg = 0;
671  if ( !retres4 )
672  {
673  VERBOSE_KPRINTF(0, "sceCdAtapi BC 1 fail\n");
674  }
675  else
676  {
677  DelayThread(10000);
678  retres4 = 0;
679  for ( i = 0; i < 100 && !retres4; i += 1 )
680  {
681  retres4 = cdvdman_169_dragon2atapi((u8 *)outbuf, &waresontmp);
682  if ( !retres4 || waresontmp )
683  DelayThread(10000);
684  }
685  if ( !retres4 )
686  {
687  VERBOSE_KPRINTF(0, "sceCdAtapi BC 2 fail\n");
688  }
689  else
690  {
691  if ( g_should_wait_for_dma_flag )
692  WaitEventFlag(g_adma_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
693  retres4 = 1;
694  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
695  memset(pkt, 0, sizeof(pkt));
696  pkt[0] = 0xF9;
697  pkt[2] = 0xB0;
698  pkt[8] = sizeof(outbuf);
699  for ( i = 0; i < 10 && retres4; i += 1 )
700  {
701  retres4 = sceCdAtapiExecCmd_local(0, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 3);
702  if ( retres4 || (retres4 = sceCdAtapiWaitResult_local()) )
703  DelayThread(10000);
704  }
705  if ( retres4 )
706  {
707  VERBOSE_KPRINTF(1, "sceCdAtapi BC 3 fail\n");
708  }
709  else
710  {
711  VERBOSE_KPRINTF(1, "sceCdAtapi BC OK\n");
712  }
713  flg = 1;
714  }
715  }
716  if ( !flg )
717  {
718  if ( g_should_wait_for_dma_flag )
719  WaitEventFlag(g_adma_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
720  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
721  }
722  }
723  }
724  {
725  char outbuf[6];
726  int retres5;
727 
728  memset(pkt, 0, sizeof(pkt));
729  retres5 = 1;
730  pkt[0] = 0xF6;
731  pkt[2] = 0xB1;
732  pkt[8] = sizeof(outbuf);
733  for ( i = 0; i < 10 && retres5; i += 1 )
734  {
735  retres5 = sceCdAtapiExecCmd_local(0, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2);
736  if ( retres5 || (retres5 = sceCdAtapiWaitResult_local()) )
737  DelayThread(10000);
738  }
739  if ( retres5 )
740  return retres4;
741  *g_cd_sc_ffffffd9_ptr = (outbuf[4] & 0x81) ? 1 : 0;
742  }
743  return retres4;
744 }
745 
746 static int atapi_spin_status_get(int unused_arg1, void *buf)
747 {
748  int result;
749  char pkt[12];
750 
751  (void)unused_arg1;
752  memset(pkt, 0, sizeof(pkt));
753  pkt[0] = 0xF6;
754  pkt[2] = 0xA0;
755  pkt[8] = 6;
756  result = xatapi_7_sceCdAtapiExecCmd(0, buf, 1, 6, pkt, sizeof(pkt), 2);
757  return (!result) ? xatapi_8_sceCdAtapiWaitResult() : result;
758 }
759 
760 static int atapi_check_if_drive_ready(int check_nowait)
761 {
762  u8 ata_control;
763  int drive_err;
764  int unitreadyctrl;
765  int senseret;
766 
767  drive_err = 0;
768  VERBOSE_KPRINTF(1, "Atapi Drive Ready Call %d\n", check_nowait);
769  ata_control = xatapi_12_get_ata_control();
770  VERBOSE_KPRINTF(1, "Atapi Drive Ready %04x\n", ata_control);
771  if ( !check_nowait )
772  {
773  int req_test_unit_ready_tmp1;
774 
775  req_test_unit_ready_tmp1 = -1;
776  while ( req_test_unit_ready_tmp1 < 0 )
777  {
778  char spinstatus_tmp[6];
779 
780  while ( (ata_control & 0xC0) != 64 )
781  {
782  VERBOSE_KPRINTF(1, "Drive Not Ready %04x\n", ata_control);
783  DelayThread(2000);
784  ata_control = xatapi_12_get_ata_control();
785  }
786  req_test_unit_ready_tmp1 = do_atapi_request_test_unit_ready(0, &drive_err, &unitreadyctrl);
787  if ( req_test_unit_ready_tmp1 < 0 )
788  DelayThread(100000);
789  if ( !atapi_req_sense_get(0, &senseret) )
790  {
791  VERBOSE_KPRINTF(1, "ReqSense %08x\n", senseret);
792  if ( (senseret & 0xFFFFFF00) == 0x23A00 )
793  break;
794  }
795  if ( !atapi_spin_status_get(0, spinstatus_tmp) )
796  {
797  VERBOSE_KPRINTF(1, "Spin Status 3:%02x 5:%02x\n", (u8)spinstatus_tmp[3], (u8)spinstatus_tmp[5]);
798  if ( (spinstatus_tmp[3] & 2) || (spinstatus_tmp[3] & 0x80) )
799  break;
800  }
801  VERBOSE_KPRINTF(1, "Atapi Drive err %08x\n", drive_err);
802  }
803  return 2;
804  }
805  return ((ata_control & 0xC0) == 64 && do_atapi_request_test_unit_ready(0, &drive_err, &unitreadyctrl) >= 0
806  && !drive_err) ?
807  2 :
808  6;
809 }
810 
811 static int sceFsDevctlBlkIO(s16 dev_nr, void *buf, void *rwbuf, unsigned int nsec, int secsize, int rwtype)
812 {
813  char *rwbuf_tmp;
814  unsigned int nsec_tmp;
815  int retres1;
816  int seccnt;
817  int i;
818  char pkt[12];
819 
820  rwbuf_tmp = (char *)rwbuf;
821  retres1 = 0;
822  VERBOSE_KPRINTF(1, "dma %c %08x, nsec %d\n", rwtype ? 'w' : 'r', rwbuf, nsec);
823  for ( nsec_tmp = nsec; !retres1 && nsec_tmp; nsec_tmp -= seccnt )
824  {
825  seccnt = (nsec_tmp >= 0x21) ? 32 : nsec_tmp;
826  for ( i = 3; i < 3; i += 1 )
827  {
828  xatapi_9_sceCdSpdAtaDmaStart(rwtype);
829  memset(pkt, 0, sizeof(pkt));
830  pkt[0] = (!rwtype) ? 0x28 : 0x2A;
831  pkt[2] = ((uiptr)rwbuf_tmp >> 24) & 0xFF;
832  pkt[3] = ((uiptr)rwbuf_tmp >> 16) & 0xFF;
833  pkt[4] = ((uiptr)rwbuf_tmp >> 8) & 0xFF;
834  pkt[5] = ((uiptr)rwbuf_tmp) & 0xFF;
835  pkt[8] = seccnt;
836  retres1 = xatapi_7_sceCdAtapiExecCmd(dev_nr, buf, seccnt, secsize, pkt, sizeof(pkt), 4);
837  if ( retres1 )
838  {
839  xatapi_10_sceCdSpdAtaDmaEnd();
840  break;
841  }
842  retres1 = xatapi_8_sceCdAtapiWaitResult();
843  xatapi_10_sceCdSpdAtaDmaEnd();
844  if ( retres1 != -510 )
845  {
846  break;
847  }
848  }
849  rwbuf_tmp += seccnt;
850  buf = (char *)buf + seccnt * secsize;
851  }
852  return retres1;
853 }
854 
855 static void expbay_device_reset(void)
856 {
857  if ( (*g_dev9_reg_power & 4) )
858  {
859  Kprintf("xatapi already Power On\n");
860  *g_dev9_reg_1460 |= 2;
861  return;
862  }
863  Kprintf("xatapi Power On Start\n");
864  *g_dev9_reg_power = (*g_dev9_reg_power & ~5) | 4;
865  DelayThread(500000);
866  *g_dev9_reg_1460 |= 2;
867  *g_dev9_reg_power |= 1;
868  DelayThread(500000);
869 }
870 
871 static int cd_atapi_intr_callback_cb(int cbarg)
872 {
873  VERBOSE_KPRINTF(1, "dev5 interrupt\n");
874  if ( p_dev5_intr_cb )
875  p_dev5_intr_cb(cbarg);
876  VERBOSE_KPRINTF(1, "dev5 interrupt end\n");
877  return 1;
878 }
879 
880 static void speedRegisterIntrDispatchCb(void *callback)
881 {
882  p_dev5_intr_cb = (int (*)(int flag))callback;
883 }
884 
885 static void sceDev5Init(void)
886 {
887  VERBOSE_KPRINTF(1, "dev5 atapi Init start\n");
888  sceCdSC(0xFFFFFFE5, (int *)cd_atapi_intr_callback_cb);
889  speed_device_init();
890  speed_init();
891  VERBOSE_KPRINTF(1, "dev5 atapi Init end\n");
892 }
893 
894 static int atapi_eject_interrupt_handler(int is_eject, void *userdata)
895 {
896  u32 buzzerres;
897 
898  (void)userdata;
899  if ( is_eject != 1 )
900  return 1;
901  VERBOSE_KPRINTF(1, "Eject intr : media removal\n");
902  return sceCdBuzzerCtl(&buzzerres);
903 }
904 
905 static int xatapi_do_init(void)
906 {
907  int (*oldcb)(int is_eject, void *userdata);
908  u32 *sc_tmp;
909  u32 trylocktmp;
910  u32 traylock_ret;
911 
912  if ( !create_event_flags() )
913  return 0;
914  sceCdSC(0xFFFFFFD9, (int *)&sc_tmp);
915  g_cd_sc_ffffffd9_ptr = sc_tmp;
916  sceCdSC(0xFFFFFFD7, (int *)&sc_tmp);
917  g_bf40200a_is_set_ptr = (int)sc_tmp;
918  oldcb = (int (*)(int is_eject, void *userdata))sceCdSetAtapiEjectCallback(
919  (int (*)(int is_eject, void *userdata))atapi_eject_interrupt_handler, 0);
920  if ( !sceCdGetMediumRemoval(&trylocktmp, &traylock_ret) )
921  {
922  VERBOSE_KPRINTF(0, "xatapi:sceCdGetMediumRemoval NG(%x) !!\n", traylock_ret);
923  trylocktmp = 0;
924  }
925  if ( trylocktmp )
926  {
927  VERBOSE_KPRINTF(0, "xatapi:Tray locked !!\n");
928  }
929  else if ( sceCdSetMediumRemoval(1, &traylock_ret) )
930  {
931  VERBOSE_KPRINTF(0, "xatapi:Tray lock\n");
932  }
933  else
934  {
935  VERBOSE_KPRINTF(0, "xatapi:Tray lock NG(%x) !!\n", traylock_ret);
936  trylocktmp = 0;
937  }
938  expbay_device_reset();
939  VERBOSE_KPRINTF(0, "xatapi Dev5->Rainbow\n");
940  sceCdChgSys(1);
941  VERBOSE_KPRINTF(1, "xatapi Dev5->Rainbow end\n");
942  VERBOSE_KPRINTF(1, "sceDev5Init Call\n");
943  sceDev5Init();
944  VERBOSE_KPRINTF(1, "sceAtInterInit Call\n");
945  sceAtInterInit();
946  VERBOSE_KPRINTF(1, "sceAtapiInit Call\n");
947  sceAtapiInit(0);
948  VERBOSE_KPRINTF(1, "sceAtapiInit end\n");
949  sceCdSC(0xFFFFFFE1, (int *)chgsys_callback_cb);
950  DelayThread(10000);
951  if ( !trylocktmp )
952  {
953  if ( !sceCdSetMediumRemoval(0, &traylock_ret) )
954  {
955  VERBOSE_KPRINTF(0, "xatapi:Tray unlock NG(%x) !!\n", traylock_ret);
956  trylocktmp = 0;
957  }
958  else
959  {
960  VERBOSE_KPRINTF(0, "xatapi:Tray unlock\n");
961  }
962  }
963  sceCdSetAtapiEjectCallback(oldcb, 0);
964  return 1;
965 }
966 
967 int xatapi_2_terminate(int with_quit)
968 {
969  int sc_tmp;
970 
971  (void)with_quit;
972  sc_tmp = 0;
973  sceCdSC(0xFFFFFFE1, &sc_tmp);
974  sceCdSC(0xFFFFFFE5, &sc_tmp);
975  sceCdSC(0xFFFFFFE0, &sc_tmp);
976  sceCdSC(0xFFFFFFDF, &sc_tmp);
977  sceCdSC(0xFFFFFFE4, &sc_tmp);
978  Kprintf("libxatapi_terminate\n");
979  return 0;
980 }
981 
982 static int xatapi_dev_devctl(
983  const iop_file_t *f, const char *name, int cmd, void *args, unsigned int arglen, void *buf, unsigned int buflen)
984 {
985  int retres1;
986  u32 efbits;
987 
988  (void)name;
989  retres1 = 0;
990  VERBOSE_KPRINTF(1, "xatapi devctl: cmd:%08x arg:%d\n", cmd, *(u32 *)args);
991  if ( cmd == 0x439B && PollEventFlag(g_io_event_flag, 1, WEF_AND, &efbits) == KE_EVF_COND && *(u32 *)args == 1 )
992  {
993  *(u32 *)buf = 6;
994  return 0;
995  }
996  WaitEventFlag(g_io_event_flag, 1, WEF_AND | WEF_CLEAR, &efbits);
997  if ( g_devctl_retonly_unset )
998  {
999  SetEventFlag(g_io_event_flag, 1);
1000  return -EIO;
1001  }
1002  switch ( cmd )
1003  {
1004  case 0x4332:
1005  retres1 = -EINVAL;
1006  if ( *(u32 *)args )
1007  {
1008  switch ( *((u32 *)args + 1) )
1009  {
1010  case 2:
1011  case 5:
1012  if ( !buflen )
1013  {
1014  retres1 = -EINVAL;
1015  break;
1016  }
1017  retres1 =
1018  xatapi_7_sceCdAtapiExecCmd(f->unit, buf, 1, buflen, (char *)args + 8, *(u32 *)args, *((u32 *)args + 1));
1019  break;
1020  case 3:
1021  case 6:
1022  if ( *((u32 *)args + 250) )
1023  {
1024  retres1 = xatapi_7_sceCdAtapiExecCmd(
1025  f->unit,
1026  (char *)args + 40,
1027  1,
1028  *((u32 *)args + 250),
1029  (char *)args + 8,
1030  *(u32 *)args,
1031  *((u32 *)args + 1));
1032  }
1033  else
1034  {
1035  retres1 = -EINVAL;
1036  }
1037  break;
1038  default:
1039  retres1 = xatapi_7_sceCdAtapiExecCmd(f->unit, 0, 0, 0, (char *)args + 8, *(u32 *)args, *((u32 *)args + 1));
1040  break;
1041  }
1042  if ( !retres1 )
1043  retres1 = xatapi_8_sceCdAtapiWaitResult();
1044  }
1045  break;
1046  case 0x4333:
1047  *(u32 *)buf = (u8)xatapi_11_sceAtaGetError();
1048  break;
1049  case 0x4334:
1050  *(u32 *)buf = (u8)xatapi_12_get_ata_control();
1051  break;
1052  case 0x4335:
1053  retres1 = sceCdAtapi_BC();
1054  if ( retres1 == 1 )
1055  retres1 = 0;
1056  break;
1057  case 0x4336:
1058  retres1 = sceCdAtapi_SC();
1059  break;
1060  case 0x4337: //?
1061  g_verbose_level = *(u32 *)args;
1062  break;
1063  case 0x4338:
1064  g_reset_scrambling_pack = *(u32 *)args;
1065  if ( g_reset_scrambling_pack )
1066  {
1067  g_pes_scrambling_control_pack = 0;
1068  }
1069  else
1070  {
1071  VERBOSE_KPRINTF(1, "pes scrambling control pack = %d\n", g_pes_scrambling_control_pack);
1072  }
1073  break;
1074  case 0x4339:
1075  DmaRun_spck((char *)args, arglen);
1076  break;
1077  case 0x433A:
1078  g_dma_mode_value = (*(u32 *)args & 0x40) ? 1 : 0;
1079  g_dma_speed_value = *(u32 *)args & 7;
1080  atapi_device_set_transfer_mode_outer(0);
1081  break;
1082  case 0x433B:
1083  if ( buf && buflen >= 2 )
1084  *(u16 *)buf = FpgaGetRevision();
1085  else
1086  Kprintf("CDIOC_ATAPI_GETFPGAREV:buffer NG\n");
1087  break;
1088  case 0x433C:
1089  if ( buf && buflen >= 4 )
1090  *(u32 *)buf = 0x4121300;
1091  else
1092  Kprintf("CDIOC_ATAPI_VERSION:buffer NG\n");
1093  break;
1094  case 0x433D:
1095  if ( buf && buflen >= 4 )
1096  *(u32 *)buf = g_pes_scrambling_control_pack;
1097  else
1098  Kprintf("CDIOC_ATAPI_GETPSCNT:buffer NG\n");
1099  break;
1100  case 0x439B:
1101  *(u32 *)buf = atapi_check_if_drive_ready(*(u32 *)args);
1102  break;
1103  case 0x4601:
1104  if ( *((u32 *)args + 3) != 2048 )
1105  {
1106  retres1 = -EINVAL;
1107  break;
1108  }
1109  VERBOSE_KPRINTF(
1110  1,
1111  "sceFsDevctlBlkIO Lsn:%d nsec:%d buffer:%08x Type:%d\n",
1112  *(u32 *)args,
1113  *((u32 *)args + 1),
1114  *((u32 *)args + 2),
1115  *((u32 *)args + 4));
1116  retres1 =
1117  sceFsDevctlBlkIO(f->unit, *((void **)args + 2), *(void **)args, *((u32 *)args + 1), 2048, *((u32 *)args + 4));
1118  break;
1119  default:
1120  Kprintf("Un-support devctl %08x\n", cmd);
1121  retres1 = -EIO;
1122  break;
1123  }
1124  SetEventFlag(g_io_event_flag, 1);
1125  VERBOSE_KPRINTF(1, "xatapi devctl: cmd:%08x End.\n", cmd);
1126  return retres1;
1127 }
1128 
1129 int _start(int ac, char **av)
1130 {
1131  (void)ac;
1132  (void)av;
1133 
1134  Kprintf("xatapi_init Call\n");
1135  // Unofficial: initialize variable here
1136  g_dma_mode_value = 1;
1137  // Unofficial: initialize variable here
1138  g_dma_speed_value = 2;
1139  if ( RegisterLibraryEntries(&_exp_xatapi) )
1140  return MODULE_NO_RESIDENT_END;
1141  DelDrv("xatapi");
1142  if ( AddDrv(&ata_ioman_device) )
1143  {
1144  // Unofficial: omitted call to empty dev deinit function
1145  return MODULE_NO_RESIDENT_END;
1146  }
1147  return !xatapi_do_init() ? MODULE_NO_RESIDENT_END : MODULE_RESIDENT_END;
1148 }
1149 
1150 static int expbay_get_has_power(void)
1151 {
1152  return *g_dev9_reg_power & 4;
1153 }
1154 
1155 static void speedRegisterIntrCb(int intr, void *cb)
1156 {
1157  g_dev5_intr_cbs[intr] = cb;
1158 }
1159 
1160 static void speedRegisterPreDmaCb(int ctrl, void *cb)
1161 {
1162  g_dev5_predma_cbs[ctrl] = cb;
1163 }
1164 
1165 static void speedRegisterPostDmaCb(int ctrl, void *cb)
1166 {
1167  g_dev5_postdma_cbs[ctrl] = cb;
1168 }
1169 
1170 static int speed_intr_dispatch(int flag)
1171 {
1172  int i;
1173  int j;
1174  USE_DEV5_SPEED_REGS();
1175 
1176  if ( flag == 1 )
1177  {
1178  AtaEjectIntrHandle();
1179  return 0;
1180  }
1181  if ( (dev5_speed_regs->r_spd_intr_stat & 0x3EFC) )
1182  {
1183  VERBOSE_KPRINTF(
1184  0, "SL3 register access failed(%x:%x) !!\n", dev5_speed_regs->r_spd_intr_stat, dev5_speed_regs->r_spd_intr_mask);
1185  return 0;
1186  }
1187  for ( i = 0; i < 3 && (u16)(dev5_speed_regs->r_spd_intr_stat & dev5_speed_regs->r_spd_intr_mask); i += 1 )
1188  {
1189  for ( j = 0; j < (int)(sizeof(g_dev5_intr_cbs) / sizeof(g_dev5_intr_cbs[0])); j += 1 )
1190  {
1191  if (
1192  g_dev5_intr_cbs[j]
1193  && (((int)(u16)(dev5_speed_regs->r_spd_intr_stat & dev5_speed_regs->r_spd_intr_mask) >> j) & 1) )
1194  g_dev5_intr_cbs[j](flag);
1195  }
1196  }
1197  return 0;
1198 }
1199 
1200 static void speedIntrEnable(s16 mask)
1201 {
1202  int state;
1203  USE_DEV5_SPEED_REGS();
1204 
1205  CpuSuspendIntr(&state);
1206  dev5_speed_regs->r_spd_intr_mask &= ~mask;
1207  dev5_speed_regs->r_spd_intr_mask |= mask;
1208  CpuResumeIntr(state);
1209 }
1210 
1211 static void speedIntrDisable(s16 mask)
1212 {
1213  int state;
1214  USE_DEV5_SPEED_REGS();
1215 
1216  CpuSuspendIntr(&state);
1217  dev5_speed_regs->r_spd_intr_mask &= ~mask;
1218  CpuResumeIntr(state);
1219 }
1220 
1221 static int SpdDmaTransfer(unsigned int device, void *buf, u32 bcr_in, int dir)
1222 {
1223  int result;
1224  USE_DEV5_SPEED_REGS();
1225 
1226  dmac_ch_set_chcr(IOP_DMAC_CDVD, 0);
1227  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1228  if ( device >= 2 && (!g_dev5_predma_cbs[device] || !g_dev5_postdma_cbs[device]) )
1229  return -1;
1230  VERBOSE_KPRINTF(1, "Wait Intr\n");
1231  result = WaitSema(g_dma_lock_sema);
1232  if ( result < 0 )
1233  return result;
1234  dev5_speed_regs->r_spd_dma_ctrl = (dev5_speed_regs->r_spd_rev_1 >= 0x11) ? ((device & 1) | 6) : ((device & 3) | 4);
1235  if ( g_dev5_predma_cbs[device] )
1236  g_dev5_predma_cbs[device](bcr_in, dir);
1237  VERBOSE_KPRINTF(1, "DMA Ch3 Set.\n");
1238  VERBOSE_KPRINTF(1, "Set MADR3:%08x Set BCR3:%08x\n", buf, bcr_in);
1239  dmac_ch_set_madr(IOP_DMAC_CDVD, (u32)buf);
1240  dmac_ch_set_bcr(IOP_DMAC_CDVD, bcr_in);
1241  dmac_ch_set_chcr(IOP_DMAC_CDVD, dir | 0x41000200);
1242  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1243  VERBOSE_KPRINTF(
1244  1,
1245  "CHCR3:%08x MADR3:%08x BCR3:%08x\n",
1246  dmac_ch_get_chcr(IOP_DMAC_CDVD),
1247  dmac_ch_get_madr(IOP_DMAC_CDVD),
1248  dmac_ch_get_bcr(IOP_DMAC_CDVD));
1249  while ( (dmac_ch_get_chcr(IOP_DMAC_CDVD) & 0x1000000) )
1250  {
1251  }
1252  VERBOSE_KPRINTF(1, "MADR3= %08x\n", dmac_ch_get_madr(IOP_DMAC_CDVD));
1253  if ( g_dev5_postdma_cbs[device] )
1254  g_dev5_postdma_cbs[device](bcr_in, dir);
1255  VERBOSE_KPRINTF(1, "SpdDmaTransfer End.\n");
1256  SignalSema(g_dma_lock_sema);
1257  return 0;
1258 }
1259 
1260 static int SpdDmaTransfer_extrans_1(unsigned int device, void *buf, u32 bcr_in, int dir)
1261 {
1262  int result;
1263  USE_DEV5_SPEED_REGS();
1264 
1265  dmac_ch_set_chcr(IOP_DMAC_CDVD, 0);
1266  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1267  if ( device >= 2 && (!g_dev5_predma_cbs[device] || !g_dev5_postdma_cbs[device]) )
1268  return -1;
1269  VERBOSE_KPRINTF(1, "Wait Intr\n");
1270  result = WaitSema(g_dma_lock_sema);
1271  if ( result < 0 )
1272  return result;
1273  dev5_speed_regs->r_spd_dma_ctrl = (dev5_speed_regs->r_spd_rev_1 >= 0x11) ? ((device & 1) | 6) : ((device & 3) | 4);
1274  if ( g_dev5_predma_cbs[device] )
1275  g_dev5_predma_cbs[device](bcr_in, dir);
1276  speedIntrDisable(256);
1277  FpgaLayer1On();
1278  FpgaXfrenOn();
1279  VERBOSE_KPRINTF(1, "DMA Ch3 Set.\n");
1280  VERBOSE_KPRINTF(1, "Set MADR3:%08x Set BCR3:%08x\n", buf, bcr_in);
1281  dmac_ch_set_madr(IOP_DMAC_CDVD, (u32)buf);
1282  dmac_ch_set_bcr(IOP_DMAC_CDVD, bcr_in);
1283  dmac_ch_set_chcr(IOP_DMAC_CDVD, dir | 0x41000200);
1284  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1285  VERBOSE_KPRINTF(
1286  1,
1287  "CHCR3:%08x MADR3:%08x BCR3:%08x\n",
1288  dmac_ch_get_chcr(IOP_DMAC_CDVD),
1289  dmac_ch_get_madr(IOP_DMAC_CDVD),
1290  dmac_ch_get_bcr(IOP_DMAC_CDVD));
1291  while ( (dmac_ch_get_chcr(IOP_DMAC_CDVD) & 0x1000000) )
1292  {
1293  }
1294  VERBOSE_KPRINTF(1, "MADR3= %08x\n", dmac_ch_get_madr(IOP_DMAC_CDVD));
1295  FpgaCheckWriteBuffer();
1296  FpgaXfrenOff();
1297  FpgaLayer1Off();
1298  speedIntrEnable(256);
1299  if ( g_dev5_postdma_cbs[device] )
1300  g_dev5_postdma_cbs[device](bcr_in, dir);
1301  VERBOSE_KPRINTF(1, "SpdDmaTransfer_extrans End.\n");
1302  SignalSema(g_dma_lock_sema);
1303  return 0;
1304 }
1305 
1306 static int SpdDmaTransfer_extrans_2(unsigned int device, void *buf, u32 bcr_in, int dir)
1307 {
1308  int result;
1309 
1310  dmac_ch_set_chcr(IOP_DMAC_CDVD, 0);
1311  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1312  if ( device >= 2 && (!g_dev5_predma_cbs[device] || !g_dev5_postdma_cbs[device]) )
1313  return -1;
1314  VERBOSE_KPRINTF(1, "Wait Intr\n");
1315  result = WaitSema(g_dma_lock_sema);
1316  if ( result < 0 )
1317  return result;
1318  VERBOSE_KPRINTF(1, "DMA Ch3 Set.\n");
1319  VERBOSE_KPRINTF(1, "Set MADR3:%08x Set BCR3:%08x\n", buf, bcr_in);
1320  dmac_ch_set_madr(IOP_DMAC_CDVD, (u32)buf);
1321  dmac_ch_set_bcr(IOP_DMAC_CDVD, bcr_in);
1322  dmac_ch_set_chcr(IOP_DMAC_CDVD, dir | 0x41000200);
1323  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1324  VERBOSE_KPRINTF(
1325  1,
1326  "CHCR3:%08x MADR3:%08x BCR3:%08x\n",
1327  dmac_ch_get_chcr(IOP_DMAC_CDVD),
1328  dmac_ch_get_madr(IOP_DMAC_CDVD),
1329  dmac_ch_get_bcr(IOP_DMAC_CDVD));
1330  while ( (dmac_ch_get_chcr(IOP_DMAC_CDVD) & 0x1000000) )
1331  {
1332  }
1333  VERBOSE_KPRINTF(1, "MADR3= %08x\n", dmac_ch_get_madr(IOP_DMAC_CDVD));
1334  VERBOSE_KPRINTF(1, "SpdDmaTransfer_extrans End.\n");
1335  SignalSema(g_dma_lock_sema);
1336  return 0;
1337 }
1338 
1339 static int SpdDmaTransfer_extrans_3(unsigned int device, void *buf, u32 bcr_in, int dir)
1340 {
1341  int result;
1342 
1343  dmac_ch_set_chcr(IOP_DMAC_CDVD, 0);
1344  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1345  if ( device >= 2 && (!g_dev5_predma_cbs[device] || !g_dev5_postdma_cbs[device]) )
1346  return -1;
1347  VERBOSE_KPRINTF(1, "Wait Intr\n");
1348  result = WaitSema(g_dma_lock_sema);
1349  if ( result < 0 )
1350  return result;
1351  FpgaLayer1On();
1352  FpgaXfrenOn();
1353  VERBOSE_KPRINTF(1, "DMA Ch3 Set.\n");
1354  VERBOSE_KPRINTF(1, "Set MADR3:%08x Set BCR3:%08x\n", buf, bcr_in);
1355  dmac_ch_set_madr(IOP_DMAC_CDVD, (u32)buf);
1356  dmac_ch_set_bcr(IOP_DMAC_CDVD, bcr_in);
1357  dmac_ch_set_chcr(IOP_DMAC_CDVD, dir | 0x41000200);
1358  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1359  VERBOSE_KPRINTF(
1360  1,
1361  "CHCR3:%08x MADR3:%08x BCR3:%08x\n",
1362  dmac_ch_get_chcr(IOP_DMAC_CDVD),
1363  dmac_ch_get_madr(IOP_DMAC_CDVD),
1364  dmac_ch_get_bcr(IOP_DMAC_CDVD));
1365  while ( (dmac_ch_get_chcr(IOP_DMAC_CDVD) & 0x1000000) )
1366  {
1367  }
1368  VERBOSE_KPRINTF(1, "MADR3= %08x\n", dmac_ch_get_madr(IOP_DMAC_CDVD));
1369  FpgaCheckWriteBuffer2();
1370  FpgaXfrenOff();
1371  FpgaLayer1Off();
1372  VERBOSE_KPRINTF(1, "SpdDmaTransfer_extrans End.\n");
1373  SignalSema(g_dma_lock_sema);
1374  return 0;
1375 }
1376 
1377 static void speedLEDCtl(int ctl)
1378 {
1379  USE_DEV5_SPEED_REGS();
1380 
1381  // Unofficial: was 8 bit access
1382  dev5_speed_regs->r_spd_pio_data = !ctl;
1383 }
1384 
1385 static void speed_init(void)
1386 {
1387  int i;
1388  iop_sema_t semaparam;
1389 
1390  semaparam.attr = SA_THPRI;
1391  semaparam.initial = 1;
1392  semaparam.max = 1;
1393  semaparam.option = 0;
1394  g_dma_lock_sema = CreateSema(&semaparam);
1395  if ( g_dma_lock_sema <= 0 )
1396  return;
1397  speedIntrDisable(0xFFFF);
1398  speedRegisterIntrDispatchCb(speed_intr_dispatch);
1399  for ( i = 0; i < (int)(sizeof(g_dev5_intr_cbs) / sizeof(g_dev5_intr_cbs[0])); i += 1 )
1400  {
1401  g_dev5_intr_cbs[i] = 0;
1402  }
1403  for ( i = 0; i < (int)(sizeof(g_dev5_predma_cbs) / sizeof(g_dev5_predma_cbs[0])); i += 1 )
1404  {
1405  g_dev5_predma_cbs[i] = 0;
1406  }
1407  for ( i = 0; i < (int)(sizeof(g_dev5_postdma_cbs) / sizeof(g_dev5_postdma_cbs[0])); i += 1 )
1408  {
1409  g_dev5_postdma_cbs[i] = 0;
1410  }
1411  speedLEDCtl(0);
1412  return;
1413 }
1414 
1415 static void speed_device_init(void)
1416 {
1417  int idx;
1418  const char *revtypes[4];
1419  USE_DEV5_SPEED_REGS();
1420 
1421  revtypes[0] = "unknown";
1422  revtypes[1] = "TS";
1423  revtypes[2] = "ES1";
1424  revtypes[3] = "ES2";
1425  switch ( dev5_speed_regs->r_spd_rev_1 )
1426  {
1427  case 9:
1428  idx = 1;
1429  break;
1430  case 16:
1431  idx = 2;
1432  break;
1433  case 17:
1434  idx = 3;
1435  break;
1436  default:
1437  idx = 0;
1438  break;
1439  }
1440  if ( idx )
1441  {
1442  VERBOSE_KPRINTF(1, "Speed chip: %s\n", revtypes[idx]);
1443  }
1444  else
1445  {
1446  VERBOSE_KPRINTF(1, "Speed chip: Rev %x\n", dev5_speed_regs->r_spd_rev_1);
1447  }
1448  VERBOSE_KPRINTF(
1449  1, "Speed version(rev3.rev8) = %04x.%04x\n", dev5_speed_regs->r_spd_rev_3, dev5_speed_regs->r_spd_rev_8);
1450 }
1451 
1452 static void do_hex_dump(void *ptr, int len)
1453 {
1454  int i;
1455  int charbuf_offs;
1456  int j;
1457  char charbuf[17];
1458 
1459  if ( !g_verbose_level )
1460  {
1461  return;
1462  }
1463  Kprintf("Hex dump 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f");
1464  j = 0;
1465  for ( i = 0; i < len; i += 256 )
1466  {
1467  for ( j = 0; j < (((len - i) > 256) ? 256 : (len - i)); j += 1 )
1468  {
1469  charbuf_offs = j & 0xF;
1470  if ( !charbuf_offs && j )
1471  {
1472  charbuf[16] = 0;
1473  Kprintf(" %s\n%08x", charbuf, i + j);
1474  }
1475  Kprintf(" %02x", (u8)((char *)ptr)[i + j]);
1476  charbuf[charbuf_offs] = (((char *)ptr)[i + j] >= 0 && isgraph(((char *)ptr)[i + j])) ? ((char *)ptr)[i + j] : '.';
1477  }
1478  }
1479  charbuf_offs = j & 0xF;
1480  for ( i = 0; (unsigned int)i < (unsigned int)((sizeof(charbuf) - 1) - charbuf_offs); i += 1 )
1481  {
1482  Kprintf("\t ");
1483  }
1484  charbuf[charbuf_offs] = 0;
1485  Kprintf("%s\n", charbuf);
1486 }
1487 
1488 static void ata_pre_dma_cb(void)
1489 {
1490  USE_DEV5_SPEED_REGS();
1491 
1492  VERBOSE_KPRINTF(1, "ata_pre_dma_handler:old %x\n", dev5_speed_regs->r_spd_xfr_ctrl);
1493  dev5_speed_regs->r_spd_xfr_ctrl |= 0x80;
1494  VERBOSE_KPRINTF(1, "ata_pre_dma_handler:new %x\n", dev5_speed_regs->r_spd_xfr_ctrl);
1495 }
1496 
1497 static void ata_post_dma_cb(void)
1498 {
1499  USE_DEV5_SPEED_REGS();
1500 
1501  VERBOSE_KPRINTF(1, "ata_post_dma_handler:old %x\n", dev5_speed_regs->r_spd_xfr_ctrl);
1502  dev5_speed_regs->r_spd_xfr_ctrl &= ~0x80;
1503  VERBOSE_KPRINTF(1, "ata_post_dma_handler:new %x\n", dev5_speed_regs->r_spd_xfr_ctrl);
1504 }
1505 
1506 static int vReferEventFlagStatus(int ef, iop_event_info_t *info)
1507 {
1508  return (QueryIntrContext()) ? iReferEventFlagStatus(ef, info) : ReferEventFlagStatus(ef, info);
1509 }
1510 
1511 void xatapi_9_sceCdSpdAtaDmaStart(int dir)
1512 {
1513  int spd_if_ctrl_manip_2;
1514  u32 efbits;
1515  USE_DEV5_SPEED_REGS();
1516 
1517  g_is_wait_busy = 0;
1518  WaitEventFlag(g_adma_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
1519  g_should_wait_for_dma_flag = 1;
1520  VERBOSE_KPRINTF(1, "sceCdSpdAtaDmaStart Call %d :Read 0:Write 1\n", dir);
1521  dev5_speed_regs->r_spd_dbuf_stat = 3;
1522  spd_if_ctrl_manip_2 = (dev5_speed_regs->r_spd_if_ctrl & 1) | (dir ? 0x4C : 0x4E);
1523  dev5_speed_regs->r_spd_if_ctrl = spd_if_ctrl_manip_2;
1524  VERBOSE_KPRINTF(1, "sceCdSpdAtaDmaStart Write R_IF_CTR:%x\n", spd_if_ctrl_manip_2);
1525  dev5_speed_regs->r_spd_xfr_ctrl = dir | 6;
1526  VERBOSE_KPRINTF(
1527  1,
1528  "sceCdSpdAtaDmaStart R_IF_CTR:%x R_XFR_CTRL:%x\n",
1529  dev5_speed_regs->r_spd_if_ctrl,
1530  dev5_speed_regs->r_spd_xfr_ctrl);
1531 }
1532 
1533 void xatapi_10_sceCdSpdAtaDmaEnd(void)
1534 {
1535  iop_event_info_t efinfo;
1536  USE_DEV5_SPEED_REGS();
1537 
1538  VERBOSE_KPRINTF(1, "sceCdSpdAtaDmaEnd Call\n");
1539  if ( !g_should_wait_for_dma_flag )
1540  {
1541  VERBOSE_KPRINTF(1, "sceCdSpdAtaDmaEnd No Start(flag)\n");
1542  return;
1543  }
1544  if ( vReferEventFlagStatus(g_adma_evfid, &efinfo) || (efinfo.currBits & 1) )
1545  {
1546  VERBOSE_KPRINTF(1, "sceCdSpdAtaDmaEnd No Start\n");
1547  g_should_wait_for_dma_flag = 0;
1548  return;
1549  }
1550  dev5_speed_regs->r_spd_xfr_ctrl = 1;
1551  dev5_speed_regs->r_spd_if_ctrl &= ~0x4;
1552  dev5_speed_regs->r_spd_dbuf_stat = 3;
1553  dev5_speed_regs->r_spd_if_ctrl &= ~0x84;
1554  dev5_speed_regs->r_spd_if_ctrl |= 0x80;
1555  dev5_speed_regs->r_spd_if_ctrl &= ~0x84;
1556  ata_pio_mode(0);
1557  if ( g_dma_mode_value )
1558  ata_ultra_dma_mode(g_dma_speed_value);
1559  else
1560  ata_multiword_dma_mode(g_dma_speed_value);
1561  g_should_wait_for_dma_flag = 0;
1562  SetEventFlag(g_adma_evfid, 1);
1563 }
1564 
1565 static void ata_pio_mode(int mode)
1566 {
1567  USE_DEV5_SPEED_REGS();
1568 
1569  VERBOSE_KPRINTF(1, "SpdAtaSetPioTiming %d\n", mode);
1570  switch ( mode )
1571  {
1572  case 0:
1573  default:
1574  dev5_speed_regs->r_spd_pio_mode = 146;
1575  break;
1576  case 1:
1577  dev5_speed_regs->r_spd_pio_mode = 114;
1578  break;
1579  case 2:
1580  dev5_speed_regs->r_spd_pio_mode = 50;
1581  break;
1582  case 3:
1583  dev5_speed_regs->r_spd_pio_mode = 36;
1584  break;
1585  case 4:
1586  dev5_speed_regs->r_spd_pio_mode = 35;
1587  break;
1588  }
1589 }
1590 
1591 static void ata_multiword_dma_mode(int mode)
1592 {
1593  USE_DEV5_SPEED_REGS();
1594 
1595  VERBOSE_KPRINTF(1, "SpdAtaSetMdmaTiming %d\n", mode);
1596  switch ( mode )
1597  {
1598  case 0:
1599  default:
1600  dev5_speed_regs->r_spd_mwdma_mode = 255;
1601  break;
1602  case 1:
1603  dev5_speed_regs->r_spd_mwdma_mode = 69;
1604  break;
1605  case 2:
1606  dev5_speed_regs->r_spd_mwdma_mode = 36;
1607  break;
1608  }
1609  dev5_speed_regs->r_spd_if_ctrl = (dev5_speed_regs->r_spd_if_ctrl & ~0x49) | 0x48;
1610 }
1611 
1612 static void ata_ultra_dma_mode(int mode)
1613 {
1614  USE_DEV5_SPEED_REGS();
1615 
1616  VERBOSE_KPRINTF(1, "SpdAtaSetUdmaTiming %d\n", mode);
1617  switch ( mode )
1618  {
1619  case 0:
1620  default:
1621  dev5_speed_regs->r_spd_udma_mode = 167;
1622  break;
1623  case 1:
1624  dev5_speed_regs->r_spd_udma_mode = 133;
1625  break;
1626  case 2:
1627  dev5_speed_regs->r_spd_udma_mode = 99;
1628  break;
1629  case 3:
1630  dev5_speed_regs->r_spd_udma_mode = 98;
1631  break;
1632  case 4:
1633  dev5_speed_regs->r_spd_udma_mode = 97;
1634  break;
1635  }
1636  dev5_speed_regs->r_spd_if_ctrl = dev5_speed_regs->r_spd_if_ctrl | 0x49;
1637 }
1638 
1639 static int ata_intr_cb(int flag)
1640 {
1641  VERBOSE_KPRINTF(1, "call AtaIntrHandle %d\n", flag);
1642  speedIntrDisable(3);
1643  iSetEventFlag(g_atapi_event_flag, 2);
1644  return 1;
1645 }
1646 
1647 static void AtaEjectIntrHandle(void)
1648 {
1649  VERBOSE_KPRINTF(1, "call AtaEjectIntrHandle\n");
1650  g_is_wait_busy = 1;
1651  iSetEventFlag(g_atapi_event_flag, 4);
1652 }
1653 
1654 static unsigned int AtaAlarmrHandle(void *usrdat)
1655 {
1656  (void)usrdat;
1657 
1658  VERBOSE_KPRINTF(1, "call AtaAlarmrHandle\n");
1659  iSetEventFlag(g_atapi_event_flag, 1);
1660  return 0;
1661 }
1662 
1663 int xatapi_14_set_speed_reg(int regaddr, u16 regval)
1664 {
1665  u32 efbits;
1666  USE_DEV5_SPEED_REGS();
1667 
1668  if ( (unsigned int)(regaddr - 64) < 0x1D )
1669  {
1670  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
1671  *(vu16 *)((char *)&dev5_speed_regs->unv00 + regaddr) = regval;
1672  SetEventFlag(g_acmd_evfid, 1);
1673  }
1674  return regval;
1675 }
1676 
1677 int xatapi_13_get_speed_reg(int regaddr)
1678 {
1679  int tmpval;
1680  u32 efbits;
1681  USE_DEV5_SPEED_REGS();
1682 
1683  if ( (unsigned int)(regaddr - 64) >= 0x1D )
1684  return 0;
1685  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
1686  tmpval = *(u16 *)((char *)&dev5_speed_regs->unv00 + regaddr);
1687  SetEventFlag(g_acmd_evfid, 1);
1688  return tmpval;
1689 }
1690 
1691 int xatapi_11_sceAtaGetError(void)
1692 {
1693  u8 r_spd_ata_error;
1694  u32 efbits;
1695  USE_DEV5_SPEED_REGS();
1696 
1697  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
1698  r_spd_ata_error = dev5_speed_regs->r_spd_ata_error;
1699  SetEventFlag(g_acmd_evfid, 1);
1700  return r_spd_ata_error;
1701 }
1702 
1703 int xatapi_12_get_ata_control(void)
1704 {
1705  u8 r_spd_ata_control;
1706  u32 efbits;
1707  USE_DEV5_SPEED_REGS();
1708 
1709  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
1710  r_spd_ata_control = dev5_speed_regs->r_spd_ata_control;
1711  SetEventFlag(g_acmd_evfid, 1);
1712  return r_spd_ata_control;
1713 }
1714 
1715 static int sceAtaGetError(void)
1716 {
1717  USE_DEV5_SPEED_REGS();
1718 
1719  return (u8)dev5_speed_regs->r_spd_ata_error;
1720 }
1721 
1722 static int ata_wait_busy1_busy(void)
1723 {
1724  unsigned int i;
1725  USE_DEV5_SPEED_REGS();
1726 
1727  for ( i = 0; i < 0x50; i += 1 )
1728  {
1729  if ( !(dev5_speed_regs->r_spd_ata_control & 0x80) )
1730  {
1731  return 0;
1732  }
1733  if ( !(u16)expbay_get_has_power() )
1734  {
1735  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busy, power off.\n");
1736  return -551;
1737  }
1738  if ( g_is_wait_busy )
1739  {
1740  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busy, tray eject.\n");
1741  return -550;
1742  }
1743  switch ( i / 0xA )
1744  {
1745  case 0:
1746  break;
1747  case 1:
1748  DelayThread(100);
1749  break;
1750  case 2:
1751  DelayThread(1000);
1752  break;
1753  case 3:
1754  DelayThread(10000);
1755  break;
1756  case 4:
1757  DelayThread(100000);
1758  break;
1759  default:
1760  DelayThread(1000000);
1761  break;
1762  }
1763  }
1764  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busy, timedout.\n", i / 0xA);
1765  return -502;
1766 }
1767 
1768 static int ata_wait_busy2_busy(void)
1769 {
1770  unsigned int i;
1771  USE_DEV5_SPEED_REGS();
1772 
1773  for ( i = 0; i < 55; i += 1 )
1774  {
1775  if ( !(dev5_speed_regs->r_spd_ata_control & 0x80) )
1776  {
1777  return 0;
1778  }
1779  if ( !(u16)expbay_get_has_power() )
1780  {
1781  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busy, power off.\n");
1782  return -551;
1783  }
1784  if ( g_is_wait_busy )
1785  {
1786  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busy, tray eject.\n");
1787  return -550;
1788  }
1789  switch ( i / 0xA )
1790  {
1791  case 0:
1792  break;
1793  case 1:
1794  DelayThread(100);
1795  break;
1796  case 2:
1797  DelayThread(1000);
1798  break;
1799  case 3:
1800  DelayThread(10000);
1801  break;
1802  case 4:
1803  DelayThread(100000);
1804  break;
1805  default:
1806  DelayThread(1000000);
1807  break;
1808  }
1809  }
1810  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busy, timedout.\n", i / 0xA);
1811  return -502;
1812 }
1813 
1814 static int ata_wait_bus_busy_busbusy(void)
1815 {
1816  unsigned int i;
1817  USE_DEV5_SPEED_REGS();
1818 
1819  for ( i = 0; i < 80; i += 1 )
1820  {
1821  if ( !(dev5_speed_regs->r_spd_ata_control & 0x88) )
1822  {
1823  return 0;
1824  }
1825  if ( !(u16)expbay_get_has_power() )
1826  {
1827  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busy, power off.\n");
1828  return -551;
1829  }
1830  if ( g_is_wait_busy )
1831  {
1832  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busbusy, tray eject.\n");
1833  return -550;
1834  }
1835  switch ( i / 0xA )
1836  {
1837  case 0:
1838  break;
1839  case 1:
1840  DelayThread(100);
1841  break;
1842  case 2:
1843  DelayThread(1000);
1844  break;
1845  case 3:
1846  DelayThread(10000);
1847  break;
1848  case 4:
1849  DelayThread(100000);
1850  break;
1851  default:
1852  DelayThread(1000000);
1853  break;
1854  }
1855  }
1856  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busbusy, timedout.\n", i / 0xA);
1857  return -502;
1858 }
1859 
1860 static int ata_device_select(int device)
1861 {
1862  int result;
1863  USE_DEV5_SPEED_REGS();
1864 
1865  result = ata_wait_bus_busy_busbusy();
1866  if ( result < 0 )
1867  {
1868  return result;
1869  }
1870  if ( ((dev5_speed_regs->r_spd_ata_select >> 4) & 1) == device )
1871  {
1872  return 0;
1873  }
1874  dev5_speed_regs->r_spd_ata_select = (device ? 1 : 0) << 4;
1875  return ata_wait_bus_busy_busbusy();
1876 }
1877 
1878 static int sceAtaExecCmd(
1879  void *buf, u32 blkcount, u16 feature, u16 nsector, u16 sector, u16 lcyl, u16 hcyl, u16 select, u16 command, u32 unk10)
1880 {
1881  int result;
1882  int using_timeout;
1883  iop_sys_clock_t sysclk;
1884  USE_DEV5_SPEED_REGS();
1885 
1886  ClearEventFlag(g_atapi_event_flag, 0);
1887  g_is_wait_busy = 0;
1888  if ( !atad_devinfo[(select & 0x10) ? 1 : 0].exists )
1889  return -505;
1890  result = ata_device_select((select >> 4) & 1);
1891  if ( result )
1892  {
1893  return result;
1894  }
1895  if ( command == 142 || command == 176 )
1896  {
1897  VERBOSE_KPRINTF(1, "Not support Ata CMD\n");
1898  return -503;
1899  }
1900  atad_cmd_state.type = unk10;
1901  if ( !unk10 )
1902  return -506;
1903  atad_cmd_state.buf = buf;
1904  atad_cmd_state.blkcount = blkcount;
1905  if (
1906  !(dev5_speed_regs->r_spd_ata_control & 0x40)
1907  && ((command < 0x90 && command != 8) || (command >= 0xA2 || command < 0xA0)) )
1908  {
1909  VERBOSE_KPRINTF(1, "DEV5 ATA: error: device not ready\n");
1910  return -501;
1911  }
1912  switch ( atad_cmd_state.type )
1913  {
1914  case 1:
1915  case 8:
1916  using_timeout = 1;
1917  break;
1918  case 4:
1919  atad_cmd_state.dir = command != 0xC8;
1920  using_timeout = 1;
1921  break;
1922  case 5:
1923  case 6:
1924  using_timeout = 1;
1925  atad_cmd_state.dir = atad_cmd_state.type != 5;
1926  break;
1927  default:
1928  using_timeout = 0;
1929  break;
1930  }
1931  if ( atad_cmd_state.type != 9 )
1932  {
1933  if ( using_timeout )
1934  {
1935  USec2SysClock((command != 142 || feature != 244) ? 155000000 : 180000000, &sysclk);
1936  result = SetAlarm(&sysclk, AtaAlarmrHandle, 0);
1937  if ( result < 0 )
1938  return result;
1939  }
1940  if ( atad_cmd_state.type == 1 )
1941  speedIntrEnable(1);
1942  dev5_speed_regs->r_spd_ata_control = (!using_timeout) << 1;
1943  }
1944  dev5_speed_regs->r_spd_ata_error = feature;
1945  dev5_speed_regs->r_spd_ata_nsector = nsector;
1946  dev5_speed_regs->r_spd_ata_sector = sector;
1947  dev5_speed_regs->r_spd_ata_lcyl = lcyl;
1948  dev5_speed_regs->r_spd_ata_hcyl = hcyl;
1949  dev5_speed_regs->r_spd_ata_select = select | 0x40;
1950  dev5_speed_regs->r_spd_ata_status = command;
1951  speedLEDCtl(1);
1952  return 0;
1953 }
1954 
1955 int xatapi_5_sceAtaExecCmd(
1956  void *buf, u32 blkcount, u16 feature, u16 nsector, u16 sector, u16 lcyl, u16 hcyl, u16 select, u16 command, u32 unk10)
1957 {
1958  int retres;
1959  u32 efbits;
1960 
1961  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
1962  retres = sceAtaExecCmd(buf, blkcount, feature, nsector, sector, lcyl, hcyl, select, command, unk10);
1963  if ( retres )
1964  {
1965  SetEventFlag(g_acmd_evfid, 1);
1966  }
1967  return retres;
1968 }
1969 
1970 static int sceCdAtapiExecCmd_local(s16 n, void *buf, int nsec, int secsize, void *pkt, unsigned int pkt_len, int proto)
1971 {
1972  u16 feature_tmp;
1973  int result;
1974  int using_timeout;
1975  int retres1;
1976  char ata_status_1;
1977  unsigned int i;
1978  iop_sys_clock_t sysclk;
1979  USE_DEV5_SPEED_REGS();
1980 
1981  feature_tmp = 0;
1982  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd Start. pkt_len %d proto %d\n", pkt_len, proto);
1983  do_hex_dump(pkt, 12);
1984  g_is_wait_busy = 0;
1985  if ( !proto )
1986  return -506;
1987  atad_cmd_state.type_atapi = proto;
1988  atad_cmd_state.buf_atapi = buf;
1989  atad_cmd_state.blkcount_atapi = nsec;
1990  atad_cmd_state.blksize_atapi = secsize;
1991  switch ( proto )
1992  {
1993  case 1:
1994  case 8:
1995  using_timeout = 1;
1996  break;
1997  case 4:
1998  switch ( *(u8 *)pkt )
1999  {
2000  case 0x03:
2001  case 0x12:
2002  case 0x23:
2003  case 0x25:
2004  case 0x28:
2005  case 0x3C:
2006  case 0x46:
2007  case 0x4A:
2008  case 0x5A:
2009  case 0xA4:
2010  case 0xA8:
2011  case 0xB9:
2012  case 0xDA:
2013  atad_cmd_state.dir_atapi = 0;
2014  break;
2015  default:
2016  atad_cmd_state.dir_atapi = 1;
2017  break;
2018  }
2019  using_timeout = 1;
2020  feature_tmp = 1;
2021  break;
2022  case 5:
2023  case 6:
2024  using_timeout = 1;
2025  feature_tmp = 1;
2026  atad_cmd_state.dir_atapi = atad_cmd_state.type_atapi != 5;
2027  break;
2028  default:
2029  using_timeout = 0;
2030  break;
2031  }
2032  if (
2033  !g_reset_scrambling_pack && atad_cmd_state.type_atapi == 4 && atad_cmd_state.dir_atapi == 1
2034  && Mpeg2CheckScramble(
2035  (char *)atad_cmd_state.buf_atapi, atad_cmd_state.blkcount_atapi * atad_cmd_state.blksize_atapi) )
2036  {
2037  VERBOSE_KPRINTF(0, "illegal stream\n");
2038  return -560;
2039  }
2040  if ( using_timeout )
2041  {
2042  USec2SysClock(0x93D1CC0, &sysclk);
2043  result = SetAlarm(&sysclk, AtaAlarmrHandle, 0);
2044  if ( result < 0 )
2045  return result;
2046  }
2047  if ( atad_cmd_state.type_atapi == 1 )
2048  speedIntrEnable(1);
2049  dev5_speed_regs->r_spd_ata_control = (!using_timeout) << 1;
2050  result = sceAtaExecCmd(
2051  0,
2052  0,
2053  feature_tmp,
2054  0,
2055  0,
2056  (u8)((atad_cmd_state.blkcount_atapi & 0xFF) * (atad_cmd_state.blksize_atapi & 0xFF)),
2057  (u8)((u16)((atad_cmd_state.blkcount_atapi & 0xFFFF) * (atad_cmd_state.blksize_atapi & 0xFFFF)) >> 8),
2058  n << 4,
2059  0xA0,
2060  9);
2061  retres1 = result;
2062  if ( retres1 )
2063  {
2064  if ( using_timeout )
2065  {
2066  CancelAlarm(AtaAlarmrHandle, 0);
2067  }
2068  return retres1;
2069  }
2070  ata_status_1 = 0;
2071  while ( (ata_status_1 & 0x88) != 8 )
2072  {
2073  int ata_status_2;
2074 
2075  DelayThread(10000);
2076  ata_status_1 = dev5_speed_regs->r_spd_ata_status;
2077  ata_status_2 = dev5_speed_regs->r_spd_ata_status;
2078  VERBOSE_KPRINTF(1, "Status 0x%02x BSY %x DRQ %x\n", ata_status_2, ata_status_1 & 0x80, ata_status_1 & 8);
2079  if ( g_is_wait_busy )
2080  {
2081  if ( using_timeout )
2082  CancelAlarm(AtaAlarmrHandle, 0);
2083  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd Tray Eject while\n", ata_status_2);
2084  return -550;
2085  }
2086  if ( !(u16)expbay_get_has_power() )
2087  {
2088  if ( using_timeout )
2089  {
2090  CancelAlarm(AtaAlarmrHandle, 0);
2091  }
2092  return -551;
2093  }
2094  }
2095  if ( (ata_status_1 & 1) )
2096  {
2097  VERBOSE_KPRINTF(1, "iocmd err 0x%02x, 0x%02x\n", ata_status_1, sceAtaGetError());
2098  if ( using_timeout )
2099  {
2100  CancelAlarm(AtaAlarmrHandle, 0);
2101  }
2102  return -503;
2103  }
2104  if ( !(ata_status_1 & 8) )
2105  {
2106  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd_local ATA_NO_DREQ\n");
2107  }
2108  for ( i = 0; i < (pkt_len >> 1); i += 1 )
2109  {
2110  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd_local Packet %04x\n", ((u16 *)pkt)[i]);
2111  dev5_speed_regs->r_spd_ata_data = ((u16 *)pkt)[i];
2112  }
2113  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd End. cmd %02x\n", *(u8 *)pkt);
2114  if ( g_is_wait_busy )
2115  {
2116  if ( using_timeout )
2117  CancelAlarm(AtaAlarmrHandle, 0);
2118  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd Tray Eject last\n", pkt_len >> 1);
2119  return -550;
2120  }
2121  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd OK\n");
2122  return 0;
2123 }
2124 
2125 static int sceCdAtapiExecCmd(s16 n, void *buf, int nsec, int secsize, void *pkt, int pkt_len, int proto)
2126 {
2127  if ( pkt_len )
2128  {
2129  int pkt_scsi_cmd_2;
2130 
2131  pkt_scsi_cmd_2 = *(u8 *)pkt;
2132  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd %08x\n", pkt_scsi_cmd_2);
2133  if (
2134  (
2135  !(pkt_scsi_cmd_2 == 0x1B || pkt_scsi_cmd_2 == 0x12 || !pkt_scsi_cmd_2 || pkt_scsi_cmd_2 == 3
2136  || *g_cd_sc_ffffffd9_ptr))
2137  && !g_is_in_read_info && !sceCdAtapi_BC() )
2138  {
2139  ata_device_set_transfer_mode_outer(0);
2140  }
2141  }
2142  return sceCdAtapiExecCmd_local(n, buf, nsec, secsize, pkt, pkt_len, proto);
2143 }
2144 
2145 int xatapi_7_sceCdAtapiExecCmd(s16 n, void *buf, int nsec, int secsize, void *pkt, int pkt_len, int proto)
2146 {
2147  int retres;
2148  u32 efbits;
2149 
2150  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
2151  retres = sceCdAtapiExecCmd(n, buf, nsec, secsize, pkt, pkt_len, proto);
2152  if ( retres )
2153  {
2154  SetEventFlag(g_acmd_evfid, 1);
2155  }
2156  return retres;
2157 }
2158 
2159 static int ata_pio_transfer(ata_cmd_state_t *cmd_state)
2160 {
2161  char r_spd_ata_status;
2162  USE_DEV5_SPEED_REGS();
2163 
2164  r_spd_ata_status = dev5_speed_regs->r_spd_ata_status;
2165  if ( (r_spd_ata_status & 1) )
2166  {
2167  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ATA PIO iocmd err 0x%02x, 0x%02x\n", r_spd_ata_status, sceAtaGetError());
2168  return -503;
2169  }
2170  else if ( (r_spd_ata_status & 8) )
2171  {
2172  int i;
2173 
2174  switch ( cmd_state->type )
2175  {
2176  case 2:
2177  {
2178  for ( i = 0; i < 256; i += 1 )
2179  {
2180  cmd_state->buf16[i] = dev5_speed_regs->r_spd_ata_data;
2181  }
2182  cmd_state->buf16 += 256;
2183  break;
2184  }
2185  case 3:
2186  {
2187  for ( i = 0; i < 256; i += 1 )
2188  {
2189  dev5_speed_regs->r_spd_ata_data = cmd_state->buf16[i];
2190  }
2191  cmd_state->buf16 += 256;
2192  break;
2193  }
2194  case 11:
2195  {
2196  for ( i = 0; i < 256; i += 1 )
2197  {
2198  dev5_speed_regs->r_spd_ata_data = cmd_state->buf16[i];
2199  }
2200  cmd_state->buf16 += 256;
2201  for ( i = 0; i < 4; i += 1 )
2202  {
2203  dev5_speed_regs->r_spd_ata_data = cmd_state->buf8[512 + i];
2204  }
2205  cmd_state->buf8 += 4;
2206  break;
2207  }
2208  default:
2209  break;
2210  }
2211  }
2212  else
2213  {
2214  return -504;
2215  }
2216  return 0;
2217 }
2218 
2219 static int IoRun_atapi(ata_cmd_state_t *cmd_state)
2220 {
2221  int result;
2222  u32 blktotal;
2223  unsigned int lhcyl;
2224  unsigned int i;
2225  USE_DEV5_SPEED_REGS();
2226 
2227  VERBOSE_KPRINTF(1, "Pio trans %d\n", cmd_state->blkcount_atapi * cmd_state->blksize_atapi);
2228  result = ata_wait_busy1_busy();
2229  if ( result < 0 )
2230  return result;
2231  result = 0;
2232  for ( blktotal = cmd_state->blkcount_atapi * cmd_state->blksize_atapi; result >= 0 && blktotal; blktotal -= lhcyl )
2233  {
2234  char r_spd_ata_status;
2235 
2236  r_spd_ata_status = dev5_speed_regs->r_spd_ata_status;
2237  if ( (r_spd_ata_status & 1) )
2238  {
2239  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ATAPI PIO iocmd err 0x%02x, 0x%02x\n", r_spd_ata_status, sceAtaGetError());
2240  return -503;
2241  }
2242  if ( !(r_spd_ata_status & 8) )
2243  return -504;
2244  // Unofficial: was 8 bit access
2245  lhcyl = (dev5_speed_regs->r_spd_ata_lcyl & 0xFF) | ((dev5_speed_regs->r_spd_ata_hcyl & 0xFF) << 8);
2246  VERBOSE_KPRINTF(1, "ByteCount Trans byte %04x\n", lhcyl);
2247  switch ( cmd_state->type_atapi )
2248  {
2249  case 2:
2250  {
2251  VERBOSE_KPRINTF(1, "IoRun_atapi input trans %d\n", cmd_state->blksize_atapi);
2252  for ( i = 0; i < (lhcyl >> 1); i += 1 )
2253  {
2254  ((u16 *)((char *)cmd_state->buf_atapi))[i] = dev5_speed_regs->r_spd_ata_data;
2255  }
2256  if ( (lhcyl & 1) )
2257  *((u8 *)cmd_state->buf_atapi + 2 * i) = dev5_speed_regs->r_spd_ata_data;
2258  cmd_state->buf_atapi = (char *)cmd_state->buf_atapi + lhcyl;
2259  break;
2260  }
2261  case 3:
2262  {
2263  VERBOSE_KPRINTF(1, "IoRun_atapi output trans %d\n", cmd_state->blksize_atapi);
2264  for ( i = 0; i < (lhcyl >> 1); i += 1 )
2265  {
2266  dev5_speed_regs->r_spd_ata_data = ((u16 *)cmd_state->buf_atapi)[i];
2267  }
2268  if ( (lhcyl & 1) )
2269  dev5_speed_regs->r_spd_ata_data = *((u8 *)cmd_state->buf_atapi + 2 * i);
2270  cmd_state->buf_atapi = (char *)cmd_state->buf_atapi + lhcyl;
2271  break;
2272  }
2273  default:
2274  break;
2275  }
2276  VERBOSE_KPRINTF(1, "IoRun_atapi trans End\n");
2277  result = ata_wait_busy1_busy();
2278  }
2279  return result;
2280 }
2281 
2282 static int atapi_transfer_wrapper(char *buf, unsigned int blkcount, int dir)
2283 {
2284  unsigned int blkcount_tmp;
2285  int i;
2286  unsigned int dbuf_stat_mask;
2287  int result;
2288  u8 Error;
2289  char spd_ata_status_tmp;
2290  u32 efbits;
2291  int flg;
2292  USE_DEV5_SPEED_REGS();
2293 
2294  for ( blkcount_tmp = blkcount; blkcount_tmp; blkcount_tmp -= (flg ? dbuf_stat_mask : 0) )
2295  {
2296  dbuf_stat_mask = 0;
2297  for ( i = 0; i < 20 && !dbuf_stat_mask; i += 1 )
2298  {
2299  dbuf_stat_mask = dev5_speed_regs->r_spd_dbuf_stat & 0x1F;
2300  }
2301  VERBOSE_KPRINTF(1, "*SPD_RINTR_STAT %02x\n", dev5_speed_regs->r_spd_intr_stat);
2302  VERBOSE_KPRINTF(1, "*R_DBUF_STAT %02x\n", dev5_speed_regs->r_spd_dbuf_stat);
2303  flg = 1;
2304  if ( !dbuf_stat_mask )
2305  {
2306  speedIntrEnable(3);
2307  VERBOSE_KPRINTF(1, "Wait Event\n");
2308  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2309  VERBOSE_KPRINTF(1, "Event come\n");
2310  if ( (efbits & 1) )
2311  {
2312  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun, ata timedout\n");
2313  return -502;
2314  }
2315  if ( (efbits & 4) )
2316  {
2317  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun, Media Eject\n");
2318  return -550;
2319  }
2320  if ( !(dev5_speed_regs->r_spd_intr_stat & 2) )
2321  {
2322  if ( (dev5_speed_regs->r_spd_ata_control & 1) )
2323  {
2324  spd_ata_status_tmp = dev5_speed_regs->r_spd_ata_status;
2325  Error = sceAtaGetError();
2326  VERBOSE_KPRINTF(1, "DEV5 ATA: error: cmd err 0x%02x, 0x%02x, while DmaRun\n", spd_ata_status_tmp, Error);
2327  return (!(Error & 0x80)) ? -503 : -510;
2328  }
2329  VERBOSE_KPRINTF(1, "DEV5 ATA: warning: ata intr without error.\n");
2330  flg = 0;
2331  }
2332  else
2333  {
2334  dbuf_stat_mask = dev5_speed_regs->r_spd_dbuf_stat & 0x1F;
2335  }
2336  }
2337  if ( flg )
2338  {
2339  if ( blkcount_tmp < dbuf_stat_mask )
2340  dbuf_stat_mask = blkcount_tmp;
2341  result = SpdDmaTransfer(0, buf, (dbuf_stat_mask << 18) | 0x20, dir);
2342  buf += dbuf_stat_mask << 9;
2343  if ( result < 0 )
2344  return result;
2345  }
2346  }
2347  return 0;
2348 }
2349 
2350 static int DmaRun_atapi(char *buf, int blkcount, int blksize, int dir)
2351 {
2352  unsigned int blkremainder;
2353  unsigned int blksectors;
2354  int i;
2355  unsigned int dbuf_stat_mask;
2356  int result;
2357  u8 Error;
2358  char spd_ata_status_tmp;
2359  unsigned int dbuf_stat_sectors;
2360  u32 efbits;
2361  USE_DEV5_SPEED_REGS();
2362 
2363  VERBOSE_KPRINTF(1, "DmaRun_atapi start\n");
2364  blkremainder = (blkcount * blksize) & 0x1FF;
2365  for ( blksectors = (unsigned int)(blkcount * blksize) >> 9; blksectors; blksectors -= dbuf_stat_mask )
2366  {
2367  dbuf_stat_mask = 0;
2368  for ( i = 0; i < 20 && !dbuf_stat_mask; i += 1 )
2369  {
2370  dbuf_stat_mask = dev5_speed_regs->r_spd_dbuf_stat & 0x1F;
2371  }
2372  if ( !dbuf_stat_mask )
2373  {
2374  speedIntrEnable(3);
2375  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2376  if ( (efbits & 1) )
2377  {
2378  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun, ata timedout\n");
2379  return -502;
2380  }
2381  if ( (efbits & 4) )
2382  {
2383  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun, Media Eject\n");
2384  return -550;
2385  }
2386  if ( (dev5_speed_regs->r_spd_intr_stat & 2) )
2387  {
2388  dbuf_stat_mask = dev5_speed_regs->r_spd_dbuf_stat & 0x1F;
2389  }
2390  else
2391  {
2392  if ( (dev5_speed_regs->r_spd_ata_control & 1) )
2393  {
2394  spd_ata_status_tmp = dev5_speed_regs->r_spd_ata_status;
2395  Error = sceAtaGetError();
2396  VERBOSE_KPRINTF(1, "DEV5 ATA: error: cmd err 0x%02x, 0x%02x, while DmaRun\n", spd_ata_status_tmp, Error);
2397  return (!(Error & 0x80)) ? -503 : -510;
2398  }
2399  VERBOSE_KPRINTF(1, "DEV5 ATA: warning: ata intr without error.\n");
2400  continue;
2401  }
2402  }
2403  if ( blksectors < dbuf_stat_mask )
2404  {
2405  dbuf_stat_mask = blksectors;
2406  }
2407  dbuf_stat_sectors = dbuf_stat_mask << 9;
2408  VERBOSE_KPRINTF(
2409  1,
2410  "DmaRun_atapi cnt %d nblk %d secsize %d bcr %08x\n",
2411  dbuf_stat_mask,
2412  blksectors,
2413  blksize,
2414  (dbuf_stat_sectors << 9) | 0x20);
2415  result = SpdDmaTransfer(0, buf, (dbuf_stat_sectors << 9) | 0x20, dir);
2416  buf += dbuf_stat_sectors;
2417  if ( result < 0 )
2418  return result;
2419  }
2420  if ( blkremainder )
2421  {
2422  while ( !(dev5_speed_regs->r_spd_intr_stat & 1) )
2423  ;
2424  dev5_speed_regs->m_spd_unk36 += 512;
2425  VERBOSE_KPRINTF(1, "SpdDmaTransfer buf:%08x bcr:%d dir:%d\n", buf, 0x40020, dir);
2426  if ( dir )
2427  {
2428  memcpy(g_atapi_xfer_buf, buf, blkremainder);
2429  result = SpdDmaTransfer(0, g_atapi_xfer_buf, 0x40020, dir);
2430  if ( result < 0 )
2431  return result;
2432  }
2433  else
2434  {
2435  result = SpdDmaTransfer(0, g_atapi_xfer_buf, 0x40020, 0);
2436  if ( result < 0 )
2437  return result;
2438  memcpy(buf, g_atapi_xfer_buf, blkremainder);
2439  }
2440  }
2441  VERBOSE_KPRINTF(1, "DmaRun_atapi End.\n");
2442  return 0;
2443 }
2444 
2445 static int DmaRun_atapi_extrans1(char *buf, int blkcount, int blksize, int dir)
2446 {
2447  unsigned int blksectors;
2448  int blkremainder;
2449  int i;
2450  unsigned int dbuf_stat_mask;
2451  int result;
2452  u8 Error;
2453  char spd_ata_status_tmp;
2454  unsigned int dbuf_stat_sectors;
2455  u32 efbits;
2456  USE_DEV5_SPEED_REGS();
2457 
2458  VERBOSE_KPRINTF(1, "DmaRun_atapi_extrans start\n");
2459  FpgaLayer2Off();
2460  FpgaClearBuffer();
2461  FpgaXfdir(dir);
2462  blkremainder = (blkcount * blksize) & 0x1FF;
2463  for ( blksectors = (unsigned int)(blkcount * blksize) >> 9; blksectors; blksectors -= dbuf_stat_mask )
2464  {
2465  dbuf_stat_mask = 0;
2466  for ( i = 0; i < 20 && !dbuf_stat_mask; i += 1 )
2467  {
2468  dbuf_stat_mask = dev5_speed_regs->r_spd_dbuf_stat & 0x1F;
2469  }
2470  if ( !dbuf_stat_mask )
2471  {
2472  speedIntrEnable(3);
2473  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2474  if ( (efbits & 1) )
2475  {
2476  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun_atapi_extrans, ata timedout\n");
2477  return -502;
2478  }
2479  if ( (efbits & 4) )
2480  {
2481  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun_atapi_extrans, Media Eject\n");
2482  return -550;
2483  }
2484  if ( (dev5_speed_regs->r_spd_intr_stat & 2) )
2485  {
2486  dbuf_stat_mask = dev5_speed_regs->r_spd_dbuf_stat & 0x1F;
2487  }
2488  else
2489  {
2490  if ( (dev5_speed_regs->r_spd_ata_control & 1) )
2491  {
2492  spd_ata_status_tmp = dev5_speed_regs->r_spd_ata_status;
2493  Error = sceAtaGetError();
2494  VERBOSE_KPRINTF(1, "DEV5 ATA: error: cmd err 0x%02x, 0x%02x, while DmaRun\n", spd_ata_status_tmp, Error);
2495  return (!(Error & 0x80)) ? -503 : -510;
2496  }
2497  VERBOSE_KPRINTF(1, "DEV5 ATA: warning: ata intr without error.\n");
2498  continue;
2499  }
2500  }
2501  if ( blksectors < dbuf_stat_mask )
2502  {
2503  dbuf_stat_mask = blksectors;
2504  }
2505  dbuf_stat_sectors = dbuf_stat_mask << 9;
2506  VERBOSE_KPRINTF(
2507  1,
2508  "DmaRun_atapi_extrans cnt %d nblk %d secsize %d bcr %08x\n",
2509  dbuf_stat_mask,
2510  blksectors,
2511  blksize,
2512  (dbuf_stat_sectors << 9) | 0x20);
2513  result = SpdDmaTransfer_extrans_1(0, buf, (dbuf_stat_sectors << 9) | 0x20, dir);
2514  buf += dbuf_stat_sectors;
2515  if ( result < 0 )
2516  return result;
2517  }
2518  if ( blkremainder )
2519  {
2520  while ( !(dev5_speed_regs->r_spd_intr_stat & 1) )
2521  ;
2522  dev5_speed_regs->m_spd_unk36 += 512;
2523  VERBOSE_KPRINTF(1, "SpdDmaTransfer buf:%08x bcr:%d dir:%d\n", buf, 0x40020, dir);
2524  if ( dir )
2525  {
2526  memcpy(g_atapi_xfer_buf, buf, blkremainder);
2527  result = SpdDmaTransfer_extrans_1(0, g_atapi_xfer_buf, 0x40020, dir);
2528  if ( result < 0 )
2529  return result;
2530  }
2531  else
2532  {
2533  result = SpdDmaTransfer_extrans_1(0, g_atapi_xfer_buf, 0x40020, 0);
2534  if ( result < 0 )
2535  return result;
2536  memcpy(buf, g_atapi_xfer_buf, blkremainder);
2537  }
2538  }
2539  VERBOSE_KPRINTF(1, "DmaRun_atapi_extrans End.\n");
2540  return 0;
2541 }
2542 
2543 static int DmaRun_atapi_extrans2(char *buf, int blkcount, int blksize, int dir)
2544 {
2545  int result;
2546  unsigned int blksectors;
2547  int blkremainder;
2548  int i;
2549  unsigned int fpga_spckcnt;
2550  u8 Error;
2551  int extransres;
2552  iop_sys_clock_t sysclk;
2553  u32 efbits;
2554  USE_DEV5_SPEED_REGS();
2555 
2556  VERBOSE_KPRINTF(1, "DmaRun_atapi_extrans start\n");
2557  FpgaLayer2Off();
2558  FpgaClearBuffer();
2559  FpgaXfdir(dir);
2560  CancelAlarm(AtaAlarmrHandle, 0);
2561  USec2SysClock(0x989680, &sysclk);
2562  result = SetAlarm(&sysclk, AtaAlarmrHandle, 0);
2563  if ( result < 0 )
2564  {
2565  return result;
2566  }
2567  while ( 1 )
2568  {
2569  speedIntrEnable(3);
2570  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2571  if ( (efbits & 1) )
2572  {
2573  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun_atapi_extrans, ata timedout\n");
2574  return -502;
2575  }
2576  if ( (efbits & 4) )
2577  {
2578  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun_atapi_extrans, Media Eject\n");
2579  return -550;
2580  }
2581  if ( (dev5_speed_regs->r_spd_intr_stat & 2) )
2582  {
2583  break;
2584  }
2585  if ( (dev5_speed_regs->r_spd_ata_control & 1) )
2586  {
2587  Error = sceAtaGetError();
2588  VERBOSE_KPRINTF(
2589  1, "DEV5 ATA: error: cmd err 0x%02x, 0x%02x, while DmaRun\n", dev5_speed_regs->r_spd_ata_status, Error);
2590  return (!(Error & 0x80)) ? -503 : -510;
2591  }
2592  VERBOSE_KPRINTF(1, "DEV5 ATA: warning: ata intr without error.\n");
2593  }
2594  dev5_speed_regs->r_spd_dma_ctrl = (dev5_speed_regs->r_spd_rev_1 >= 0x11) ? 6 : 4;
2595  ata_pre_dma_cb();
2596  FpgaLayer1On();
2597  FpgaXfrenOn();
2598  blkremainder = (blkcount * blksize) & 0x1FF;
2599  extransres = 0;
2600  for ( blksectors = (unsigned int)(blkcount * blksize) >> 9; blksectors; blksectors -= fpga_spckcnt )
2601  {
2602  unsigned int fpga_spckcnt_bytes;
2603 
2604  for ( i = 0;; i += 1 )
2605  {
2606  fpga_spckcnt = do_fpga_check_spckcnt();
2607  if ( fpga_spckcnt >= 3 || fpga_spckcnt >= blksectors )
2608  break;
2609  switch ( i / 500 )
2610  {
2611  case 0:
2612  break;
2613  case 1:
2614  DelayThread(100);
2615  break;
2616  default:
2617  DelayThread(10000);
2618  break;
2619  }
2620  PollEventFlag(g_atapi_event_flag, 5, WEF_OR | WEF_CLEAR, &efbits);
2621  if ( (efbits & 1) )
2622  {
2623  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun_atapi_extrans, ata timedout\n");
2624  FpgaXfrenOff();
2625  FpgaLayer1Off();
2626  ata_post_dma_cb();
2627  if ( !(dev5_speed_regs->r_spd_intr_stat & 2) && (dev5_speed_regs->r_spd_ata_control & 1) )
2628  {
2629  Error = sceAtaGetError();
2630  VERBOSE_KPRINTF(
2631  1, "DEV5 ATA: error: cmd err 0x%02x, 0x%02x, while DmaRun\n", dev5_speed_regs->r_spd_ata_status, Error);
2632  return (!(Error & 0x80)) ? -503 : -510;
2633  }
2634  return -502;
2635  }
2636  if ( (efbits & 4) )
2637  {
2638  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun_atapi_extrans, Media Eject\n");
2639  FpgaXfrenOff();
2640  FpgaLayer1Off();
2641  ata_post_dma_cb();
2642  return -550;
2643  }
2644  }
2645  if ( blksectors < fpga_spckcnt )
2646  {
2647  fpga_spckcnt = blksectors;
2648  }
2649  fpga_spckcnt_bytes = fpga_spckcnt << 9;
2650  VERBOSE_KPRINTF(
2651  1,
2652  "DmaRun_atapi_extrans cnt %d nblk %d secsize %d bcr %08x\n",
2653  fpga_spckcnt,
2654  blksectors,
2655  blksize,
2656  (fpga_spckcnt_bytes << 9) | 0x20);
2657  extransres = SpdDmaTransfer_extrans_2(0, buf, (fpga_spckcnt_bytes << 9) | 0x20, dir);
2658  if ( extransres < 0 )
2659  break;
2660  buf += fpga_spckcnt_bytes;
2661  }
2662  FpgaXfrenOff();
2663  FpgaLayer1Off();
2664  ata_post_dma_cb();
2665  if ( extransres >= 0 && blkremainder )
2666  {
2667  while ( !(dev5_speed_regs->r_spd_intr_stat & 1) )
2668  ;
2669  dev5_speed_regs->m_spd_unk36 += 512;
2670  VERBOSE_KPRINTF(1, "SpdDmaTransfer buf:%08x bcr:%d dir:%d\n", buf, 0x40020, dir);
2671  ata_pre_dma_cb();
2672  FpgaLayer1On();
2673  FpgaXfrenOn();
2674  if ( dir )
2675  {
2676  memcpy(g_atapi_xfer_buf, buf, blkremainder);
2677  extransres = SpdDmaTransfer_extrans_2(0, g_atapi_xfer_buf, 0x40020, dir);
2678  }
2679  else
2680  {
2681  extransres = SpdDmaTransfer_extrans_2(0, g_atapi_xfer_buf, 0x40020, 0);
2682  if ( extransres >= 0 )
2683  {
2684  memcpy(buf, g_atapi_xfer_buf, blkremainder);
2685  }
2686  }
2687  FpgaXfrenOff();
2688  FpgaLayer1Off();
2689  ata_post_dma_cb();
2690  }
2691  if ( extransres < 0 )
2692  {
2693  return extransres;
2694  }
2695  VERBOSE_KPRINTF(1, "DmaRun_atapi_extrans End.\n");
2696  return 0;
2697 }
2698 
2699 static void DmaRun_spck(char *buf, unsigned int secsize)
2700 {
2701  unsigned int secsize_sectors;
2702  unsigned int fpga_spckcnt;
2703  USE_DEV5_SPEED_REGS();
2704 
2705  VERBOSE_KPRINTF(1, "DmaRun_spck start\n");
2706  FpgaSpckmodeOn();
2707  FpgaLayer2Off();
2708  FpgaClearBuffer();
2709  FpgaXfdir(0);
2710  for ( secsize_sectors = secsize >> 9; secsize_sectors; secsize_sectors -= fpga_spckcnt )
2711  {
2712  unsigned int fpga_spckcnt_bytes;
2713 
2714  for ( fpga_spckcnt = 0; fpga_spckcnt < 4; fpga_spckcnt = do_fpga_check_spckcnt() )
2715  ;
2716  if ( secsize_sectors < fpga_spckcnt )
2717  {
2718  fpga_spckcnt = secsize_sectors;
2719  }
2720  fpga_spckcnt_bytes = fpga_spckcnt << 9;
2721  VERBOSE_KPRINTF(
2722  1,
2723  "DmaRun_spck cnt %d nblk %d secsize %d bcr %08x\n",
2724  fpga_spckcnt,
2725  secsize_sectors,
2726  secsize,
2727  (fpga_spckcnt_bytes << 9) | 0x20);
2728  if ( SpdDmaTransfer_extrans_3(0, buf, (fpga_spckcnt_bytes << 9) | 0x20, 1) < 0 )
2729  {
2730  FpgaSpckmodeOff();
2731  return;
2732  }
2733  buf += fpga_spckcnt_bytes;
2734  }
2735  if ( (secsize & 0x1FF) )
2736  {
2737  dev5_speed_regs->m_spd_unk36 += 512;
2738  VERBOSE_KPRINTF(1, "SpdDmaTransfer buf:%08x bcr:%d dir:%d\n", buf, 0x40020, 1);
2739  memcpy(g_atapi_xfer_buf, buf, secsize & 0x1FF);
2740  if ( SpdDmaTransfer_extrans_3(0, g_atapi_xfer_buf, 0x40020, 1) < 0 )
2741  {
2742  return;
2743  }
2744  }
2745  FpgaSpckmodeOff();
2746  VERBOSE_KPRINTF(1, "DmaRun_spck End.\n");
2747 }
2748 
2749 static int sceAtaWaitResult(void)
2750 {
2751  int res;
2752  int i;
2753  int intr_stat_msk;
2754  u32 efbits;
2755  int suc;
2756  USE_DEV5_SPEED_REGS();
2757 
2758  suc = 0;
2759  res = 0;
2760  switch ( atad_cmd_state.type )
2761  {
2762  case 1:
2763  case 8:
2764  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2765  if ( (efbits & 1) )
2766  {
2767  res = -502;
2768  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ata timedout while non data command\n");
2769  }
2770  if ( (efbits & 4) )
2771  {
2772  res = -550;
2773  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun, Media Eject\n");
2774  }
2775  suc = 1;
2776  break;
2777  case 4:
2778  case 5:
2779  case 6:
2780  res = atapi_transfer_wrapper((char *)atad_cmd_state.buf, atad_cmd_state.blkcount, atad_cmd_state.dir);
2781  if ( res )
2782  {
2783  break;
2784  }
2785  intr_stat_msk = 0;
2786  for ( i = 0; i < 100 && !intr_stat_msk; i += 1 )
2787  {
2788  intr_stat_msk = dev5_speed_regs->r_spd_intr_stat & 1;
2789  }
2790  if ( !intr_stat_msk )
2791  {
2792  speedIntrEnable(1);
2793  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2794  if ( (efbits & 1) )
2795  {
2796  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ata timedout, buffer stat %04x\n", dev5_speed_regs->r_spd_dbuf_stat);
2797  VERBOSE_KPRINTF(
2798  1,
2799  "DEV5 ATA: error: istat %x, ienable %x\n",
2800  dev5_speed_regs->r_spd_intr_stat,
2801  dev5_speed_regs->r_spd_intr_mask);
2802  res = -502;
2803  }
2804  if ( (efbits & 4) )
2805  {
2806  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ata eject, buffer stat %04x\n", dev5_speed_regs->r_spd_dbuf_stat);
2807  VERBOSE_KPRINTF(
2808  1,
2809  "DEV5 ATA: error: istat %x, ienable %x\n",
2810  dev5_speed_regs->r_spd_intr_stat,
2811  dev5_speed_regs->r_spd_intr_mask);
2812  res = -550;
2813  }
2814  }
2815  suc = 1;
2816  break;
2817  default:
2818  while ( 1 )
2819  {
2820  res = ata_wait_busy1_busy();
2821  if ( res < 0 )
2822  {
2823  break;
2824  }
2825  atad_cmd_state.blkcount -= 1;
2826  if ( atad_cmd_state.blkcount == 0xFFFFFFFF )
2827  {
2828  suc = 1;
2829  break;
2830  }
2831  res = ata_pio_transfer(&atad_cmd_state);
2832  if ( res < 0 )
2833  {
2834  break;
2835  }
2836  }
2837  break;
2838  }
2839  if ( suc && !res )
2840  {
2841  char status_tmp;
2842 
2843  status_tmp = dev5_speed_regs->r_spd_ata_status;
2844  if ( (status_tmp & 0x80) )
2845  {
2846  res = ata_wait_busy1_busy();
2847  status_tmp = dev5_speed_regs->r_spd_ata_status;
2848  }
2849  if ( (status_tmp & 1) )
2850  {
2851  u8 Error;
2852 
2853  Error = sceAtaGetError();
2854  VERBOSE_KPRINTF(1, "DEV5 ATA: error: cmd err 0x%02x, 0x%02x\n", status_tmp, Error);
2855  res = (Error & 0x80) ? -510 : -503;
2856  }
2857  }
2858  CancelAlarm(AtaAlarmrHandle, 0);
2859  speedLEDCtl(0);
2860  if ( res )
2861  {
2862  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ATA failed, %d\n", res);
2863  }
2864  return res;
2865 }
2866 
2867 int xatapi_6_sceAtaWaitResult(void)
2868 {
2869  int restmp;
2870  iop_event_info_t efinfo;
2871 
2872  if ( vReferEventFlagStatus(g_acmd_evfid, &efinfo) || (efinfo.currBits & 1) )
2873  {
2874  VERBOSE_KPRINTF(1, "sceCdAtapiWaitResult Call Error\n");
2875  return -511;
2876  }
2877  restmp = sceAtaWaitResult();
2878  SetEventFlag(g_acmd_evfid, 1);
2879  return restmp;
2880 }
2881 
2882 static int sceCdAtapiWaitResult_local(void)
2883 {
2884  int res;
2885  int i;
2886  int intr_stat_msk;
2887  u32 efbits;
2888  int padinfo;
2889  USE_DEV5_SPEED_REGS();
2890 
2891  res = 0;
2892  switch ( atad_cmd_state.type_atapi )
2893  {
2894  case 1:
2895  case 8:
2896  VERBOSE_KPRINTF(1, "waitresult\n");
2897  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2898  if ( (efbits & 1) )
2899  {
2900  res = -502;
2901  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ata timedout while non data command\n");
2902  }
2903  if ( (efbits & 4) )
2904  {
2905  res = -550;
2906  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ata eject while non data command\n");
2907  }
2908  break;
2909  case 4:
2910  case 5:
2911  case 6:
2912  VERBOSE_KPRINTF(1, "waitresult dma\n");
2913  if ( !g_reset_scrambling_pack )
2914  {
2915  res = DmaRun_atapi(
2916  (char *)atad_cmd_state.buf_atapi,
2917  atad_cmd_state.blkcount_atapi,
2918  atad_cmd_state.blksize_atapi,
2919  atad_cmd_state.dir_atapi);
2920  }
2921  else if ( atad_cmd_state.dir_atapi )
2922  {
2923  int blktotal1;
2924  int blkoffs;
2925 
2926  blktotal1 = atad_cmd_state.blkcount_atapi * atad_cmd_state.blksize_atapi;
2927  for ( blkoffs = 0; blkoffs < blktotal1;
2928  blkoffs += atad_cmd_state.blkcount_atapi * atad_cmd_state.blksize_atapi )
2929  {
2930  int padres;
2931 
2932  padres = Mpeg2CheckPadding(
2933  (char *)atad_cmd_state.buf_atapi + blkoffs, blktotal1 - blkoffs, &padinfo, &g_pes_scrambling_control_pack);
2934  if ( padres < 0 )
2935  {
2936  res = DmaRun_atapi(
2937  (char *)atad_cmd_state.buf_atapi,
2938  atad_cmd_state.blkcount_atapi,
2939  atad_cmd_state.blksize_atapi,
2940  atad_cmd_state.dir_atapi);
2941  break;
2942  }
2943  atad_cmd_state.blksize_atapi = 2048;
2944  atad_cmd_state.blkcount_atapi = padinfo;
2945  res = padres ?
2946  DmaRun_atapi_extrans1(
2947  (char *)atad_cmd_state.buf_atapi + blkoffs, padinfo, 2048, atad_cmd_state.dir_atapi) :
2948  DmaRun_atapi((char *)atad_cmd_state.buf_atapi + blkoffs, padinfo, 2048, atad_cmd_state.dir_atapi);
2949  }
2950  }
2951  else
2952  {
2953  res = DmaRun_atapi_extrans2(
2954  (char *)atad_cmd_state.buf_atapi, atad_cmd_state.blkcount_atapi, atad_cmd_state.blksize_atapi, 0);
2955  }
2956  if ( res )
2957  {
2958  break;
2959  }
2960  intr_stat_msk = 0;
2961  for ( i = 0; i < 100 && !intr_stat_msk; i += 1 )
2962  {
2963  intr_stat_msk = dev5_speed_regs->r_spd_intr_stat & 1;
2964  }
2965  if ( intr_stat_msk )
2966  {
2967  break;
2968  }
2969  VERBOSE_KPRINTF(1, "ata command not finished yet\n");
2970  speedIntrEnable(1);
2971  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2972  if ( (efbits & 1) )
2973  {
2974  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ata timedout, buffer stat %04x\n", dev5_speed_regs->r_spd_dbuf_stat);
2975  VERBOSE_KPRINTF(
2976  1,
2977  "DEV5 ATA: error: istat %x, ienable %x\n",
2978  dev5_speed_regs->r_spd_intr_stat,
2979  dev5_speed_regs->r_spd_intr_mask);
2980  res = -502;
2981  }
2982  if ( (efbits & 4) )
2983  {
2984  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ata eject, buffer stat %04x\n", dev5_speed_regs->r_spd_dbuf_stat);
2985  VERBOSE_KPRINTF(
2986  1,
2987  "DEV5 ATA: error: istat %x, ienable %x\n",
2988  dev5_speed_regs->r_spd_intr_stat,
2989  dev5_speed_regs->r_spd_intr_mask);
2990  res = -550;
2991  }
2992  break;
2993  default:
2994  res = IoRun_atapi(&atad_cmd_state);
2995  break;
2996  }
2997  if ( !res )
2998  {
2999  char ata_status_tmp;
3000 
3001  ata_status_tmp = dev5_speed_regs->r_spd_ata_status;
3002  if ( (ata_status_tmp & 0x80) )
3003  {
3004  res = ata_wait_busy1_busy();
3005  ata_status_tmp = dev5_speed_regs->r_spd_ata_status;
3006  }
3007  if ( (ata_status_tmp & 1) )
3008  {
3009  u8 Error;
3010 
3011  Error = sceAtaGetError();
3012  VERBOSE_KPRINTF(1, "DEV5 ATA: error: cmd status 0x%02x, error 0x%02x\n", ata_status_tmp, Error);
3013  res = (Error & 0x80) ? -510 : -503;
3014  }
3015  }
3016  CancelAlarm(AtaAlarmrHandle, 0);
3017  speedLEDCtl(0);
3018  VERBOSE_KPRINTF(1, "sceCdAtapiWaitResult_local() End.\n");
3019  if ( res )
3020  {
3021  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ATA failed, %d\n", res);
3022  }
3023  return res;
3024 }
3025 
3026 int xatapi_8_sceCdAtapiWaitResult(void)
3027 {
3028  int restmp;
3029  iop_event_info_t efinfo;
3030 
3031  if ( vReferEventFlagStatus(g_acmd_evfid, &efinfo) || (efinfo.currBits & 1) )
3032  {
3033  VERBOSE_KPRINTF(1, "sceCdAtapiWaitResult Call Error\n");
3034  return -511;
3035  }
3036  restmp = sceCdAtapiWaitResult_local();
3037  SetEventFlag(g_acmd_evfid, 1);
3038  return restmp;
3039 }
3040 
3041 static void ata_bus_reset_inner(void)
3042 {
3043  USE_DEV5_SPEED_REGS();
3044 
3045  dev5_speed_regs->r_spd_if_ctrl = 128;
3046  DelayThread(100);
3047  dev5_speed_regs->r_spd_if_ctrl = 0;
3048  dev5_speed_regs->r_spd_if_ctrl = 72;
3049  DelayThread(3000);
3050  VERBOSE_KPRINTF(1, "hard reset\n");
3051 }
3052 
3053 static int ata_bus_reset(void)
3054 {
3055  USE_DEV5_SPEED_REGS();
3056 
3057  if ( !(dev5_speed_regs->r_spd_if_ctrl & 0x40) )
3058  ata_bus_reset_inner();
3059  return ata_wait_busy2_busy();
3060 }
3061 
3062 int xatapi_4_sceAtaSoftReset(void)
3063 {
3064  USE_DEV5_SPEED_REGS();
3065 
3066  if ( (dev5_speed_regs->r_spd_ata_control & 0x80) )
3067  return -501;
3068  dev5_speed_regs->r_spd_ata_control = 6;
3069  DelayThread(100);
3070  dev5_speed_regs->r_spd_ata_control = 2;
3071  DelayThread(3000);
3072  VERBOSE_KPRINTF(1, "soft reset\n");
3073  return ata_wait_busy1_busy();
3074 }
3075 
3076 #ifdef UNUSED_FUNC
3077 static int sceAtaFlushCache(int device)
3078 {
3079  int result;
3080 
3081  result = xatapi_5_sceAtaExecCmd(0, 1, 0, 0, 0, 0, 0, device << 4, 0xE7, 1);
3082  return result ? result : xatapi_6_sceAtaWaitResult();
3083 }
3084 #endif
3085 
3086 static int ata_device_identify(int device, void *info)
3087 {
3088  int result;
3089 
3090  result = xatapi_5_sceAtaExecCmd(info, 1, 0, 0, 0, 0, 0, device << 4, 0xEC, 2);
3091  return result ? result : xatapi_6_sceAtaWaitResult();
3092 }
3093 
3094 static int ata_device_pkt_identify(int device, void *info)
3095 {
3096  int result;
3097 
3098  result = xatapi_5_sceAtaExecCmd(info, 1, 0, 0, 0, 0, 0, device << 4, 0xA1, 2);
3099  return result ? result : xatapi_6_sceAtaWaitResult();
3100 }
3101 
3102 static int atapi_device_set_transfer_mode(int device, int type, int mode)
3103 {
3104  int result;
3105 
3106  result = xatapi_5_sceAtaExecCmd(0, 1, 3, (u8)(mode | type), 0, 0, 0, device << 4, 0xEF, 1);
3107  if ( result )
3108  return result;
3109  result = xatapi_6_sceAtaWaitResult();
3110  if ( result )
3111  return result;
3112  switch ( type )
3113  {
3114  case 8:
3115  ata_pio_mode(mode);
3116  break;
3117  case 0x20:
3118  ata_multiword_dma_mode(mode);
3119  break;
3120  case 0x40:
3121  ata_ultra_dma_mode(mode);
3122  break;
3123  default:
3124  break;
3125  }
3126  return 0;
3127 }
3128 
3129 static int ata_device_set_transfer_mode(int device, int type, int mode)
3130 {
3131  int result;
3132 
3133  result = sceAtaExecCmd(0, 1, 3, (u8)(mode | type), 0, 0, 0, device << 4, 0xEF, 1);
3134  if ( result )
3135  return result;
3136  result = sceAtaWaitResult();
3137  if ( result )
3138  return result;
3139  switch ( type )
3140  {
3141  case 8:
3142  ata_pio_mode(mode);
3143  break;
3144  case 32:
3145  ata_multiword_dma_mode(mode);
3146  break;
3147  case 64:
3148  ata_ultra_dma_mode(mode);
3149  break;
3150  default:
3151  break;
3152  }
3153  return 0;
3154 }
3155 
3156 static void ata_device_probe(ata_devinfo_t *devinfo)
3157 {
3158  char r_spd_ata_lcyl;
3159  u8 r_spd_ata_hcyl;
3160  USE_DEV5_SPEED_REGS();
3161 
3162  devinfo->exists = 0;
3163  devinfo->has_packet = 2;
3164  if ( (dev5_speed_regs->r_spd_ata_control & 0x88) )
3165  {
3166  VERBOSE_KPRINTF(1, "FindDev ATA_BUSY\n");
3167  return;
3168  }
3169  r_spd_ata_lcyl = dev5_speed_regs->r_spd_ata_lcyl;
3170  r_spd_ata_hcyl = dev5_speed_regs->r_spd_ata_hcyl;
3171  if ( dev5_speed_regs->r_spd_ata_nsector != 1 || dev5_speed_regs->r_spd_ata_sector != 1 )
3172  {
3173  VERBOSE_KPRINTF(1, "FindDev ATA_NOT_CONNECT\n");
3174  return;
3175  }
3176  devinfo->exists = 1;
3177  if ( !r_spd_ata_lcyl && !r_spd_ata_hcyl )
3178  devinfo->has_packet = 0;
3179  if ( r_spd_ata_lcyl == 20 && r_spd_ata_hcyl == 235 )
3180  devinfo->has_packet = 1;
3181  dev5_speed_regs->r_spd_ata_lcyl = 85;
3182  dev5_speed_regs->r_spd_ata_hcyl = 170;
3183  // Unofficial: was 8 bit access
3184  // cppcheck-suppress knownConditionTrueFalse
3185  if ( (dev5_speed_regs->r_spd_ata_lcyl & 0xFF) != 85 || (dev5_speed_regs->r_spd_ata_hcyl & 0xFF) != 170 )
3186  devinfo->exists = 0;
3187 }
3188 
3189 static void atapi_device_set_transfer_mode_outer(int device)
3190 {
3191  if ( g_dma_mode_value )
3192  {
3193  VERBOSE_KPRINTF(0, "UDMA_mode Mode%d\n", 2);
3194  while ( atapi_device_set_transfer_mode(device, 64, (u8)g_dma_speed_value) < 0 )
3195  {
3196  DelayThread(2000000);
3197  }
3198  }
3199  else
3200  {
3201  VERBOSE_KPRINTF(0, "MDMA_mode Mode%d\n", 2);
3202  while ( atapi_device_set_transfer_mode(device, 32, (u8)g_dma_speed_value) < 0 )
3203  {
3204  DelayThread(2000000);
3205  }
3206  }
3207 }
3208 
3209 static void ata_device_set_transfer_mode_outer(int device)
3210 {
3211  int i;
3212 
3213  if ( g_dma_mode_value )
3214  {
3215  VERBOSE_KPRINTF(0, "UDMA_mode Mode%d\n", 2);
3216  for ( i = 0; i < 3 && ata_device_set_transfer_mode(device, 64, (u8)g_dma_speed_value); i += 1 )
3217  {
3218  DelayThread(2000000);
3219  }
3220  }
3221  else
3222  {
3223  VERBOSE_KPRINTF(0, "MDMA_mode Mode%d\n", 2);
3224  for ( i = 0; i < 3 && ata_device_set_transfer_mode(device, 32, (u8)g_dma_speed_value); i += 1 )
3225  {
3226  DelayThread(2000000);
3227  }
3228  }
3229 }
3230 
3231 static void ata_init_devices(ata_devinfo_t *devinfo)
3232 {
3233  int i;
3234  USE_DEV5_SPEED_REGS();
3235 
3236  if ( xatapi_4_sceAtaSoftReset() )
3237  return;
3238  ata_device_probe(&devinfo[0]);
3239  if ( !devinfo[0].exists )
3240  {
3241  VERBOSE_KPRINTF(1, "DEV5 ATA: error: there is no device0\n");
3242  devinfo[1].exists = 0;
3243  return;
3244  }
3245  if ( ata_device_select(1) )
3246  return;
3247  // Unofficial: was 8 bit access
3248  if ( (dev5_speed_regs->r_spd_ata_control & 0xFF) )
3249  ata_device_probe(&devinfo[1]);
3250  else
3251  devinfo[1].exists = 0;
3252  ata_pio_mode(0);
3253  g_is_in_read_info = 0;
3254  for ( i = 0; i < 2; i += 1 )
3255  {
3256  if ( !devinfo[i].exists )
3257  {
3258  continue;
3259  }
3260  if ( !devinfo[i].has_packet )
3261  {
3262  devinfo[i].exists = !ata_device_identify(i, ata_param);
3263  }
3264  if ( devinfo[i].has_packet == 1 )
3265  devinfo[i].exists = !ata_device_pkt_identify(i, ata_param);
3266  VERBOSE_KPRINTF(1, "device%d connected, kind %d.\n", i, devinfo[i].has_packet);
3267  if ( !devinfo[i].exists || devinfo[i].has_packet != 1 )
3268  {
3269  continue;
3270  }
3271  do_hex_dump(ata_param, sizeof(ata_param));
3272  devinfo[i].lba48 = !do_atapi_cmd_inquiry_12h(i);
3273  if ( devinfo[i].lba48 )
3274  {
3275  g_is_in_read_info = 1;
3276  VERBOSE_KPRINTF(0, "Atapi Program Aria Brokun.\n");
3277  continue;
3278  }
3279  atapi_device_set_transfer_mode_outer(i);
3280  }
3281 }
3282 
3283 static void sceAtapiInit(int device)
3284 {
3285  int resetval;
3286  USE_DEV5_SPEED_REGS();
3287 
3288  (void)device;
3289  if ( g_ata_devinfo_init )
3290  return;
3291  g_ata_devinfo_init = 1;
3292  while ( 1 )
3293  {
3294  while ( 1 )
3295  {
3296  resetval = ata_bus_reset();
3297  if ( resetval != -550 )
3298  break;
3299  g_is_wait_busy = 0;
3300  }
3301  if ( !resetval )
3302  break;
3303  dev5_speed_regs->r_spd_if_ctrl = 0;
3304  }
3305  ata_init_devices(atad_devinfo);
3306 }
3307 
3308 static void sceAtInterInit(void)
3309 {
3310  int sc_tmp;
3311 
3312  speedRegisterIntrCb(1, ata_intr_cb);
3313  speedRegisterIntrCb(0, ata_intr_cb);
3314  speedRegisterPreDmaCb(0, ata_pre_dma_cb);
3315  speedRegisterPostDmaCb(0, ata_post_dma_cb);
3316  if ( sceCdSC(0xFFFFFFDC, &sc_tmp) )
3317  speedIntrEnable(256);
3318 }
3319 
3320 static int create_event_flags(void)
3321 {
3322  iop_event_t efparam;
3323 
3324  efparam.attr = EA_SINGLE;
3325  efparam.bits = 0;
3326  g_atapi_event_flag = CreateEventFlag(&efparam);
3327  if ( g_atapi_event_flag < 0 )
3328  return 1;
3329  efparam.attr = EA_MULTI;
3330  efparam.option = 0;
3331  efparam.bits = 1;
3332  g_acmd_evfid = CreateEventFlag(&efparam);
3333  if ( g_acmd_evfid >= 0 )
3334  {
3335  efparam.bits = 1;
3336  g_adma_evfid = CreateEventFlag(&efparam);
3337  if ( g_adma_evfid >= 0 )
3338  {
3339  efparam.bits = 1;
3340  g_io_event_flag = CreateEventFlag(&efparam);
3341  if ( g_io_event_flag >= 0 )
3342  {
3343  sceCdSC(0xFFFFFFE0, &g_acmd_evfid);
3344  sceCdSC(0xFFFFFFDF, &g_adma_evfid);
3345  return 1;
3346  }
3347  }
3348  }
3349  if ( g_atapi_event_flag >= 0 )
3350  DeleteEventFlag(g_atapi_event_flag);
3351  if ( g_acmd_evfid >= 0 )
3352  DeleteEventFlag(g_acmd_evfid);
3353  if ( g_adma_evfid >= 0 )
3354  DeleteEventFlag(g_adma_evfid);
3355  return 0;
3356 }
3357 
3358 static void FpgaLayer1On(void)
3359 {
3360  USE_DEV5_FPGA_REGS();
3361  VERBOSE_KPRINTF(1, "%s():old:FPGA_LAYER1 %x\n", "FpgaLayer1On", dev5_fpga_regs->r_fpga_layer1);
3362  dev5_fpga_regs->r_fpga_layer1 &= ~1;
3363  dev5_fpga_regs->r_fpga_layer1 |= 1;
3364  VERBOSE_KPRINTF(1, "%s():new:FPGA_LAYER1 %x\n", "FpgaLayer1On", dev5_fpga_regs->r_fpga_layer1);
3365 }
3366 
3367 static void FpgaLayer1Off(void)
3368 {
3369  USE_DEV5_FPGA_REGS();
3370 
3371  VERBOSE_KPRINTF(1, "%s():old:FPGA_LAYER1 %x\n", "FpgaLayer1Off", dev5_fpga_regs->r_fpga_layer1);
3372  dev5_fpga_regs->r_fpga_layer1 &= ~1;
3373  VERBOSE_KPRINTF(1, "%s():new:FPGA_LAYER1 %x\n", "FpgaLayer1Off", dev5_fpga_regs->r_fpga_layer1);
3374 }
3375 
3376 #ifdef UNUSED_FUNC
3377 static void FpgaLayer2On(void)
3378 {
3379  USE_DEV5_FPGA_REGS();
3380 
3381  VERBOSE_KPRINTF(1, "%s():old:FPGA_LAYER2 %x\n", "FpgaLayer2On", dev5_fpga_regs->r_fpga_layer2);
3382  dev5_fpga_regs->r_fpga_layer2 &= ~1;
3383  dev5_fpga_regs->r_fpga_layer2 |= 1;
3384  VERBOSE_KPRINTF(1, "%s():new:FPGA_LAYER2 %x\n", "FpgaLayer2On", dev5_fpga_regs->r_fpga_layer2);
3385 }
3386 #endif
3387 
3388 static void FpgaLayer2Off(void)
3389 {
3390  USE_DEV5_FPGA_REGS();
3391 
3392  VERBOSE_KPRINTF(1, "%s():old:FPGA_LAYER2 %x\n", "FpgaLayer2Off", dev5_fpga_regs->r_fpga_layer2);
3393  dev5_fpga_regs->r_fpga_layer2 &= ~1;
3394  VERBOSE_KPRINTF(1, "%s():new:FPGA_LAYER2 %x\n", "FpgaLayer2Off", dev5_fpga_regs->r_fpga_layer2);
3395 }
3396 
3397 static void FpgaXfrenOn(void)
3398 {
3399  USE_DEV5_FPGA_REGS();
3400 
3401  VERBOSE_KPRINTF(1, "%s():old:FPGA_XFREN %x\n", "FpgaXfrenOn", dev5_fpga_regs->r_fpga_xfren);
3402  dev5_fpga_regs->r_fpga_xfren &= ~1;
3403  dev5_fpga_regs->r_fpga_xfren |= 1;
3404  VERBOSE_KPRINTF(1, "%s():new:FPGA_XFREN %x\n", "FpgaXfrenOn", dev5_fpga_regs->r_fpga_xfren);
3405 }
3406 
3407 static void FpgaXfrenOff(void)
3408 {
3409  USE_DEV5_FPGA_REGS();
3410 
3411  VERBOSE_KPRINTF(1, "%s():old:FPGA_XFREN %x\n", "FpgaXfrenOff", dev5_fpga_regs->r_fpga_xfren);
3412  dev5_fpga_regs->r_fpga_xfren &= ~1;
3413  VERBOSE_KPRINTF(1, "%s():new:FPGA_XFREN %x\n", "FpgaXfrenOff", dev5_fpga_regs->r_fpga_xfren);
3414 }
3415 
3416 static void FpgaSpckmodeOn(void)
3417 {
3418  USE_DEV5_FPGA_REGS();
3419 
3420  VERBOSE_KPRINTF(1, "%s():old:FPGA_SPCKMODE %x\n", "FpgaSpckmodeOn", dev5_fpga_regs->r_fpga_spckmode);
3421  dev5_fpga_regs->r_fpga_spckmode &= ~1;
3422  dev5_fpga_regs->r_fpga_spckmode |= 1;
3423  VERBOSE_KPRINTF(1, "%s():new:FPGA_SPCKMODE %x\n", "FpgaSpckmodeOn", dev5_fpga_regs->r_fpga_spckmode);
3424 }
3425 
3426 static void FpgaSpckmodeOff(void)
3427 {
3428  USE_DEV5_FPGA_REGS();
3429 
3430  VERBOSE_KPRINTF(1, "%s():old:FPGA_SPCKMODE %x\n", "FpgaSpckmodeOff", dev5_fpga_regs->r_fpga_spckmode);
3431  dev5_fpga_regs->r_fpga_spckmode &= ~1;
3432  VERBOSE_KPRINTF(1, "%s():new:FPGA_SPCKMODE %x\n", "FpgaSpckmodeOff", dev5_fpga_regs->r_fpga_spckmode);
3433 }
3434 
3435 static void FpgaXfdir(int dir)
3436 {
3437  USE_DEV5_FPGA_REGS();
3438 
3439  VERBOSE_KPRINTF(1, "%s():old:FPGA_XFRDIR %x\n", "FpgaXfrdir", dev5_fpga_regs->r_fpga_xfrdir);
3440  dev5_fpga_regs->r_fpga_xfrdir &= ~1;
3441  if ( dir )
3442  {
3443  dev5_fpga_regs->r_fpga_xfrdir |= 1;
3444  }
3445  VERBOSE_KPRINTF(1, "%s():new:FPGA_XFRDIR %x\n", "FpgaXfrdir", dev5_fpga_regs->r_fpga_xfrdir);
3446 }
3447 
3448 static int FpgaGetRevision(void)
3449 {
3450  USE_DEV5_FPGA_REGS();
3451 
3452  VERBOSE_KPRINTF(1, "%s():FPGA_REVISION %x\n", "FpgaGetRevision", dev5_fpga_regs->r_fpga_revision);
3453  return (u16)dev5_fpga_regs->r_fpga_revision;
3454 }
3455 
3456 #ifdef UNUSED_FUNC
3457 static unsigned int do_fpga_add_unused8120(void)
3458 {
3459  USE_DEV5_FPGA_REGS();
3460 
3461  return (dev5_fpga_regs->r_fpga_sl3bufd + (unsigned int)dev5_fpga_regs->r_fpga_exbufd) >> 7;
3462 }
3463 #endif
3464 
3465 static int do_fpga_check_spckcnt(void)
3466 {
3467  USE_DEV5_FPGA_REGS();
3468 
3469  return (u16)dev5_fpga_regs->r_fpga_spckcnt;
3470 }
3471 
3472 static void FpgaCheckWriteBuffer(void)
3473 {
3474  int i;
3475  USE_DEV5_FPGA_REGS();
3476 
3477  VERBOSE_KPRINTF(1, "%s():in ...\n", "FpgaCheckWriteBuffer");
3478  for ( i = 0; i < 10000 && (dev5_fpga_regs->r_fpga_exbufe || dev5_fpga_regs->r_fpga_sl3bufe); i += 1 )
3479  ;
3480  if ( i == 10000 )
3481  {
3482  VERBOSE_KPRINTF(0, "exbuf enc=%x, sl3buf enc=%x\n", dev5_fpga_regs->r_fpga_exbufe, dev5_fpga_regs->r_fpga_sl3bufe);
3483  }
3484  VERBOSE_KPRINTF(1, "%s():out ...\n", "FpgaCheckWriteBuffer");
3485 }
3486 
3487 static void FpgaCheckWriteBuffer2(void)
3488 {
3489  USE_DEV5_FPGA_REGS();
3490 
3491  VERBOSE_KPRINTF(1, "%s():in ...\n", "FpgaCheckWriteBuffer2");
3492  while ( dev5_fpga_regs->r_fpga_sl3bufd )
3493  {
3494  VERBOSE_KPRINTF(1, "%s():FPGA_SL3BUFD %x\n", "FpgaCheckWriteBuffer2", dev5_fpga_regs->r_fpga_sl3bufd);
3495  VERBOSE_KPRINTF(1, "%s():FPGA_SL3BUFE %x\n", "FpgaCheckWriteBuffer2", dev5_fpga_regs->r_fpga_sl3bufe);
3496  VERBOSE_KPRINTF(1, "%s():FPGA_EXBUFD %x\n", "FpgaCheckWriteBuffer2", dev5_fpga_regs->r_fpga_exbufd);
3497  VERBOSE_KPRINTF(1, "%s():FPGA_EXBUFE %x\n", "FpgaCheckWriteBuffer2", dev5_fpga_regs->r_fpga_exbufe);
3498  }
3499  VERBOSE_KPRINTF(1, "%s():out ...\n", "FpgaCheckWriteBuffer2");
3500 }
3501 
3502 static void FpgaClearBuffer(void)
3503 {
3504  USE_DEV5_FPGA_REGS();
3505 
3506  VERBOSE_KPRINTF(1, "%s():old:FPGA_SL3BUFD %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_sl3bufd);
3507  VERBOSE_KPRINTF(1, "%s():old:FPGA_SL3BUFE %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_sl3bufe);
3508  VERBOSE_KPRINTF(1, "%s():old:FPGA_EXBUFD %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_exbufd);
3509  VERBOSE_KPRINTF(1, "%s():old:FPGA_EXBUFE %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_exbufe);
3510  dev5_fpga_regs->r_fpga_unk30 &= ~1;
3511  dev5_fpga_regs->r_fpga_unk30 |= 1;
3512  while ( (u16)(dev5_fpga_regs->r_fpga_exbufd) || dev5_fpga_regs->r_fpga_sl3bufd )
3513  ;
3514  while ( dev5_fpga_regs->r_fpga_exbufe || dev5_fpga_regs->r_fpga_sl3bufe )
3515  ;
3516  dev5_fpga_regs->r_fpga_unk30 &= ~1;
3517  VERBOSE_KPRINTF(1, "%s():new:FPGA_SL3BUFD %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_sl3bufd);
3518  VERBOSE_KPRINTF(1, "%s():new:FPGA_SL3BUFE %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_sl3bufe);
3519  VERBOSE_KPRINTF(1, "%s():new:FPGA_EXBUFD %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_exbufd);
3520  VERBOSE_KPRINTF(1, "%s():new:FPGA_EXBUFE %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_exbufe);
3521 }
3522 
3523 static int Mpeg2CheckPadding(char *buf, unsigned int bufsize, int *retptr, int *pesscramblingpackptr)
3524 {
3525  int bufchk;
3526  char *bufoffs1;
3527  const char *bufoffs2;
3528  int i;
3529 
3530  bufchk = 0;
3531  VERBOSE_KPRINTF(1, "%s():in\n", "Mpeg2CheckPadding");
3532  if ( (bufsize & 0x7FF) )
3533  {
3534  VERBOSE_KPRINTF(1, "%s():Buffer size not aligne !!\n", "Mpeg2CheckPadding");
3535  return -1;
3536  }
3537  if ( !*buf && !buf[1] && buf[2] == 1 && (u8)buf[3] == 0xBA )
3538  bufchk = 1;
3539  for ( i = 0; (unsigned int)i < (bufsize >> 11); i += 1 )
3540  {
3541  bufoffs1 = &buf[i << 11];
3542  if ( *bufoffs1 || bufoffs1[1] || bufoffs1[2] != 1 || (u8)bufoffs1[3] != 0xBA )
3543  {
3544  if ( bufchk )
3545  break;
3546  }
3547  else
3548  {
3549  if ( !bufchk )
3550  break;
3551  bufoffs2 = bufoffs1 + 14;
3552  if ( !bufoffs1[14] )
3553  {
3554  if ( !bufoffs1[15] && bufoffs1[16] == 1 && (u8)bufoffs1[17] == 0xBB )
3555  bufoffs2 = bufoffs1 + 38;
3556  if ( !*bufoffs2 && !bufoffs2[1] && bufoffs2[2] == 1 && (u8)bufoffs2[3] != 0xBF && (bufoffs2[6] & 0x60) )
3557  {
3558  *pesscramblingpackptr += 1;
3559  }
3560  }
3561  }
3562  }
3563  VERBOSE_KPRINTF(1, "%s():out %d %s Pack\n", "Mpeg2CheckPadding", i, bufchk ? "RDI" : "NULL");
3564  *retptr = i;
3565  return bufchk;
3566 }
3567 
3568 static int Mpeg2CheckScramble(char *buf, unsigned int bufsize)
3569 {
3570  int restmp;
3571  signed int i;
3572  char *bufcur;
3573  const char *bufbuf;
3574  int buf3;
3575 
3576  restmp = 0;
3577  VERBOSE_KPRINTF(1, "%s():in\n", "Mpeg2CheckScramble");
3578  if ( (bufsize & 0x7FF) )
3579  {
3580  VERBOSE_KPRINTF(1, "%s():Buffer size not aligne !!\n", "Mpeg2CheckScramble");
3581  return 0;
3582  }
3583  for ( i = 0; i < (int)(bufsize >> 11); i += 1 )
3584  {
3585  bufcur = buf + (i << 11);
3586  if ( !*bufcur && !bufcur[1] && bufcur[2] == 1 && (u8)bufcur[3] == 0xBA )
3587  {
3588  bufbuf = bufcur + 14;
3589  if ( !bufcur[14] )
3590  {
3591  if ( !bufcur[15] && bufcur[16] == 1 && (u8)bufcur[17] == 0xBB )
3592  bufbuf = bufcur + 38;
3593  if ( !*bufbuf && !bufbuf[1] && bufbuf[2] == 1 )
3594  {
3595  buf3 = (u8)bufbuf[3];
3596  if ( (buf3 == 0xE0 || buf3 == 0xBD || buf3 == 0xC0 || buf3 == 0xD0) && (bufbuf[6] & 0x30) )
3597  {
3598  restmp = 0xFFFFFFFF;
3599  break;
3600  }
3601  }
3602  }
3603  }
3604  }
3605  VERBOSE_KPRINTF(1, "%s():out\n", "Mpeg2CheckScramble");
3606  return restmp;
3607 }
dev5_fpga_regs_
Definition: xatapi.c:113
sceCdGetMediumRemoval
int sceCdGetMediumRemoval(u32 *result1, u32 *result2)
IOP_DT_FSEXT
#define IOP_DT_FSEXT
Definition: iomanX.h:66
_ata_devinfo::has_packet
s32 has_packet
Definition: xatapi.c:42
cdvdman_169_dragon2atapi
int cdvdman_169_dragon2atapi(u8 *outbuf, u32 *status)
_ata_devinfo
Definition: xatapi.c:39
iop_sema_t
Definition: thsemap.h:38
s_info
Definition: xprintf.c:78
EA_MULTI
#define EA_MULTI
Definition: thevent.h:35
_ata_cmd_state
Definition: xatapi.c:21
QueryIntrContext
int QueryIntrContext(void)
xatapi.h
CpuSuspendIntr
int CpuSuspendIntr(int *state)
Definition: intrman.c:195
iop_event_info_t::currBits
u32 currBits
Definition: thevent.h:53
EIO
#define EIO
Definition: errno.h:29
sceCdSetAtapiEjectCallback
void * sceCdSetAtapiEjectCallback(int(*cb)(int reason, void *userdata), void *userdata)
_ata_devinfo::security_status
u32 security_status
Definition: xatapi.c:44
_ata_devinfo::exists
s32 exists
Definition: xatapi.c:41
dev5_speed_regs_
Definition: xatapi.c:48
cdvdman_167_atapi2dragon
int cdvdman_167_atapi2dragon(u8 *inbuf, u32 *status)
irx_export_table
Definition: irx.h:90
sceCdChgSys
int sceCdChgSys(u32 arg1)
_iop_file::unit
int unit
Definition: ioman.h:57
_iop_file
Definition: ioman.h:53
CpuResumeIntr
int CpuResumeIntr(int state)
Definition: intrman.c:217
_ata_devinfo::total_sectors
u32 total_sectors
Definition: xatapi.c:43
_iop_device_ops
Definition: ioman.h:79
iop_event_info_t
Definition: thevent.h:44
EINVAL
#define EINVAL
Definition: errno.h:63
sceCdSetMediumRemoval
int sceCdSetMediumRemoval(u8 arg1, u32 *result)
_iop_device
Definition: ioman.h:64
_ata_devinfo::lba48
u32 lba48
Definition: xatapi.c:45
iop_event_t
Definition: thevent.h:37
sceCdBuzzerCtl
int sceCdBuzzerCtl(u32 *result)
EA_SINGLE
#define EA_SINGLE
Definition: thevent.h:33
_iop_sys_clock
Definition: thbase.h:87
errno.h
kerr.h