PS2SDK
PS2 Homebrew Libraries
xatapi.c
1 /*
2 # _____ ___ ____ ___ ____
3 # ____| | ____| | | |____|
4 # | ___| |____ ___| ____| | \ PS2DEV Open Source Project.
5 #-----------------------------------------------------------------------
6 # Copyright ps2dev - http://www.ps2dev.org
7 # Licenced under Academic Free License version 2.0
8 # Review ps2sdk README & LICENSE files for further details.
9 */
10 
11 #include "irx_imports.h"
12 #include <errno.h>
13 #include <kerr.h>
14 #include <xatapi.h>
15 #include <blkio-ioctl.h>
16 
17 #ifdef _IOP
18 IRX_ID("cdvd_xatapi_driver", 2, 3);
19 #endif
20 // Based off of DESR / PSX DVR system software version 2.11.
21 
22 typedef struct _ata_cmd_state
23 {
24  s32 type;
25  union
26  {
27  void *buf;
28  u8 *buf8;
29  u16 *buf16;
30  };
31  u32 blkcount;
32  s32 dir;
33  s32 type_atapi;
34  void *buf_atapi;
35  u32 blkcount_atapi;
36  u32 blksize_atapi;
37  s32 dir_atapi;
38 } ata_cmd_state_t;
39 
40 typedef struct _ata_devinfo
41 {
42  s32 exists;
43  s32 has_packet;
44  u32 total_sectors;
45  u32 security_status;
46  u32 lba48;
47 } ata_devinfo_t;
48 
49 struct dev5_speed_regs_
50 {
51  vu16 unv00;
52  vu16 r_spd_rev_1;
53  vu16 r_spd_rev_3;
54  vu16 unv06;
55  vu16 unv08;
56  vu16 unv0a;
57  vu16 unv0c;
58  vu16 r_spd_rev_8;
59  vu16 unv10;
60  vu16 unv12;
61  vu16 unv14;
62  vu16 unv16;
63  vu16 unv18;
64  vu16 unv1a;
65  vu16 unv1c;
66  vu16 unv1e;
67  vu16 unv20;
68  vu16 unv22;
69  vu16 r_spd_dma_ctrl;
70  vu16 unv26;
71  vu16 r_spd_intr_stat;
72  vu16 r_spd_intr_mask;
73  vu16 unv2c;
74  vu16 r_spd_pio_data;
75  vu16 unv30;
76  vu16 r_spd_xfr_ctrl;
77  vu16 unv34;
78  vu16 m_spd_unk36;
79  vu16 r_spd_dbuf_stat;
80  vu16 unv3a;
81  vu16 unv3c;
82  vu16 unv3e;
83  vu16 r_spd_ata_data;
84  vu16 r_spd_ata_error;
85  vu16 r_spd_ata_nsector;
86  vu16 r_spd_ata_sector;
87  vu16 r_spd_ata_lcyl;
88  vu16 r_spd_ata_hcyl;
89  vu16 r_spd_ata_select;
90  vu16 r_spd_ata_status;
91  vu16 unv50;
92  vu16 unv52;
93  vu16 unv54;
94  vu16 unv56;
95  vu16 unv58;
96  vu16 unv5a;
97  vu16 r_spd_ata_control;
98  vu16 unv5e;
99  vu16 unv60;
100  vu16 unv62;
101  vu16 r_spd_if_ctrl;
102  vu16 unv66;
103  vu16 unv68;
104  vu16 unv6a;
105  vu16 unv6c;
106  vu16 unv6e;
107  vu16 r_spd_pio_mode;
108  vu16 r_spd_mwdma_mode;
109  vu16 r_spd_udma_mode;
110 };
111 // cppcheck-suppress-macro constVariablePointer
112 #define USE_DEV5_SPEED_REGS() struct dev5_speed_regs_ *const dev5_speed_regs = (void *)0xBF410000
113 
114 struct dev5_fpga_regs_
115 {
116  vu16 r_fpga_layer1;
117  vu16 r_fpga_xfrdir;
118  vu16 r_fpga_xfren;
119  vu16 r_fpga_layer2;
120  vu16 r_fpga_sl3bufe;
121  vu16 r_fpga_sl3bufd;
122  vu16 unv0c;
123  vu16 unv0e;
124  vu16 unv10;
125  vu16 r_fpga_exbufd;
126  vu16 r_fpga_exbufe;
127  vu16 unv16;
128  vu16 unv18;
129  vu16 unv1a;
130  vu16 unv1c;
131  vu16 unv1e;
132  vu16 unv20;
133  vu16 unv22;
134  vu16 unv24;
135  vu16 unv26;
136  vu16 unv28;
137  vu16 unv2a;
138  vu16 unv2c;
139  vu16 unv2e;
140  vu16 r_fpga_unk30;
141  vu16 r_fpga_spckmode;
142  vu16 r_fpga_spckcnt;
143  vu16 unvpad[2013];
144  vu16 r_fpga_revision;
145 };
146 // cppcheck-suppress-macro constVariablePointer
147 #define USE_DEV5_FPGA_REGS() struct dev5_fpga_regs_ *const dev5_fpga_regs = (void *)0xBF414000
148 
149 static int xatapi_dev_devctl(
150  const iop_file_t *f, const char *name, int cmd, void *args, unsigned int arglen, void *buf, unsigned int buflen);
151 static void speed_init(void);
152 static void speed_device_init(void);
153 static void do_hex_dump(void *ptr, int len);
154 static void ata_pio_mode(int mode);
155 static void ata_multiword_dma_mode(int mode);
156 static void ata_ultra_dma_mode(int mode);
157 static void AtaEjectIntrHandle(void);
158 static int sceCdAtapiExecCmd_local(s16 n, void *buf, int nsec, int secsize, void *pkt, unsigned int pkt_len, int proto);
159 static int sceCdAtapiExecCmd(s16 n, void *buf, int nsec, int secsize, void *pkt, int pkt_len, int proto);
160 static void DmaRun_spck(char *buf, unsigned int secsize);
161 static int sceCdAtapiWaitResult_local(void);
162 static void atapi_device_set_transfer_mode_outer(int device);
163 static void ata_device_set_transfer_mode_outer(int device);
164 static void sceAtapiInit(int device);
165 static void sceAtInterInit(void);
166 static int create_event_flags(void);
167 static void FpgaLayer1On(void);
168 static void FpgaLayer1Off(void);
169 static void FpgaLayer2Off(void);
170 static void FpgaXfrenOn(void);
171 static void FpgaXfrenOff(void);
172 static void FpgaSpckmodeOn(void);
173 static void FpgaSpckmodeOff(void);
174 static void FpgaXfdir(int dir);
175 static int FpgaGetRevision(void);
176 static int do_fpga_check_spckcnt(void);
177 static void FpgaCheckWriteBuffer(void);
178 static void FpgaCheckWriteBuffer2(void);
179 static void FpgaClearBuffer(void);
180 static int Mpeg2CheckPadding(char *buf, unsigned int bufsize, int *retptr, int *pesscramblingpackptr);
181 static int Mpeg2CheckScramble(char *buf, unsigned int bufsize);
182 
183 extern struct irx_export_table _exp_xatapi;
184 // Unofficial: move to bss
185 static int g_devctl_retonly_unset;
186 static vu16 *const g_dev9_reg_1460 = (void *)0xBF801460;
187 static vu16 *const g_dev9_reg_power = (void *)0xBF80146C;
188 // Unofficial: move to bss
189 static int (*p_dev5_intr_cb)(int flag);
190 
191 // cppcheck-suppress unusedFunction
192 IOMANX_RETURN_VALUE_IMPL(0);
193 // unofficial: don't print on nulldev0 call
194 IOMANX_RETURN_VALUE_IMPL(EIO);
195 
196 static iop_device_ops_t ata_ioman_devops = {
197  IOMANX_RETURN_VALUE(0), IOMANX_RETURN_VALUE(0), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO),
198  IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO),
199  IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO),
200  IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO),
201  IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO),
202  IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE_S64(EIO), (void *)&xatapi_dev_devctl,
203  IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO), IOMANX_RETURN_VALUE(EIO),
204 };
205 static iop_device_t ata_ioman_device = {"xatapi", IOP_DT_FS | IOP_DT_FSEXT, 1, "CD-ROM_ATAPI", &ata_ioman_devops};
206 // Unofficial: move to bss
207 static int g_reset_scrambling_pack;
208 // Unofficial: move to bss
209 static int g_pes_scrambling_control_pack;
210 // Unofficial: move to bss
211 static int g_dma_mode_value;
212 // Unofficial: move to bss
213 static int g_dma_speed_value;
214 // Unofficial: move to bss
215 static int g_should_wait_for_dma_flag;
216 // Unofficial: move to bss
217 static int g_is_wait_busy;
218 // Unofficial: move to bss
219 static int g_verbose_level;
220 // Unofficial: move to bss
221 static int g_ata_devinfo_init;
222 static int g_bf40200a_is_set_ptr;
223 static u32 *g_cd_sc_ffffffd9_ptr;
224 static int g_is_in_read_info;
225 static int g_io_event_flag;
226 static int g_adma_evfid;
227 static int g_acmd_evfid;
228 static int g_dma_lock_sema;
229 static void (*g_dev5_intr_cbs[16])(int flag);
230 static void (*g_dev5_predma_cbs[4])(u32 bcr_in, int dir);
231 static void (*g_dev5_postdma_cbs[4])(u32 bcr_in, int dir);
232 static int g_atapi_event_flag;
233 static ata_devinfo_t atad_devinfo[2];
234 static ata_cmd_state_t atad_cmd_state;
235 static int ata_param[128];
236 static int g_atapi_xfer_buf[130];
237 
238 static int do_atapi_cmd_inquiry_12h(s16 dev_nr)
239 {
240  int i;
241  int retres;
242  char pkt[12];
243  char outbuf[56];
244 
245  retres = 1;
246  for ( i = 0; retres && i < 16; i += 1 )
247  {
248  memset(pkt, 0, sizeof(pkt));
249  pkt[0] = 0x12;
250  pkt[4] = sizeof(outbuf);
251  retres = sceCdAtapiExecCmd_local(dev_nr, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2);
252  if ( retres )
253  continue;
254  retres = sceCdAtapiWaitResult_local();
255  if ( retres )
256  {
257  VERBOSE_KPRINTF(1, "Atapi Drive ATAPI_CMD_READ_EXT_INFO NG\n");
258  DelayThread(10000);
259  }
260  }
261  if ( retres )
262  return retres;
263  do_hex_dump(outbuf, sizeof(outbuf));
264  return strncmp(&outbuf[32], "BOOT", 4) ? 1 : 0;
265 }
266 
267 static int do_atapi_request_test_unit_ready(s16 dev_nr, int *errptr, int *ctrlptr)
268 {
269  int retres;
270  char pkt[12];
271 
272  *errptr = 0;
273  *ctrlptr = 0;
274  memset(pkt, 0, sizeof(pkt));
275  pkt[0] = 0;
276  retres = xatapi_7_sceCdAtapiExecCmd(dev_nr, 0, 0, 0, pkt, sizeof(pkt), 1);
277  if ( retres )
278  return retres;
279  retres = xatapi_8_sceCdAtapiWaitResult();
280  *errptr = (u8)xatapi_11_sceAtaGetError();
281  *ctrlptr = (u8)xatapi_12_get_ata_control();
282  return retres;
283 }
284 
285 static int atapi_req_sense_get(s16 dev_nr, int *retptr)
286 {
287  int result;
288  char pkt[12];
289  char outbuf[18];
290 
291  *retptr = 0;
292  memset(pkt, 0, sizeof(pkt));
293  pkt[0] = 3;
294  pkt[4] = sizeof(outbuf);
295  result = xatapi_7_sceCdAtapiExecCmd(dev_nr, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2);
296  if ( result )
297  return result;
298  result = xatapi_8_sceCdAtapiWaitResult();
299  if ( result )
300  return result;
301  *retptr = ((outbuf[2] & 0xF) << 16) | ((u8)outbuf[12] << 8) | (u8)outbuf[13];
302  return 0;
303 }
304 
305 #ifdef UNUSED_FUNC
306 static int atapi_exec_cmd_request_sense_03h_unused(s16 dev_nr, int *retptr)
307 {
308  int result;
309  char pkt[12];
310  char outbuf[18];
311 
312  *retptr = 0;
313  memset(pkt, 0, sizeof(pkt));
314  pkt[0] = 3;
315  pkt[4] = sizeof(outbuf);
316  result = sceCdAtapiExecCmd_local(dev_nr, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2);
317  if ( result )
318  return result;
319  result = sceCdAtapiWaitResult_local();
320  if ( result )
321  return result;
322  *retptr = ((outbuf[2] & 0xF) << 16) | ((u8)outbuf[12] << 8) | (u8)outbuf[13];
323  return 0;
324 }
325 #endif
326 
327 #ifdef UNUSED_FUNC
328 static int do_start_stop_unit_1bh_unused(void)
329 {
330  int i;
331  int retres;
332  char pkt[12];
333 
334  retres = 1;
335  for ( i = 0; i < 16 && retres && retres != -550; i += 1 )
336  {
337  memset(pkt, 0, sizeof(pkt));
338  pkt[0] = 0x1B;
339  pkt[4] = 2;
340  pkt[5] = 0;
341  retres = sceCdAtapiExecCmd_local(0, 0, 0, 0, pkt, sizeof(pkt), 1);
342  if ( retres )
343  continue;
344  retres = sceCdAtapiWaitResult_local();
345  if ( retres )
346  {
347  VERBOSE_KPRINTF(1, "Atapi Drive EJECT NG\n");
348  DelayThread(10000);
349  continue;
350  }
351  VERBOSE_KPRINTF(1, "Atapi Drive EJECT OK\n");
352  }
353  if ( !retres )
354  {
355  retres = 1;
356  for ( i = 0; i < 16 && retres && retres != -550; i += 1 )
357  {
358  memset(pkt, 0, sizeof(pkt));
359  pkt[0] = 0x1B;
360  pkt[4] = 3;
361  pkt[5] = 0;
362  retres = sceCdAtapiExecCmd_local(0, 0, 0, 0, pkt, sizeof(pkt), 1);
363  if ( retres )
364  continue;
365  retres = sceCdAtapiWaitResult_local();
366  if ( retres )
367  {
368  VERBOSE_KPRINTF(1, "Atapi Drive Spindle Start NG %d\n", i);
369  DelayThread(10000);
370  continue;
371  }
372  VERBOSE_KPRINTF(1, "Atapi Drive Spindle Start OK\n");
373  }
374  }
375  VERBOSE_KPRINTF(1, " PS2 Eject On Atapi Unit Dummy Eject Ret %d\n", retres);
376  return retres;
377 }
378 #endif
379 
380 static int chgsys_callback_cb(int *mediaptr, int want_atapi)
381 {
382  int i;
383  int tryres1;
384  int retres;
385  char pkt[12];
386  char outbuf1[6];
387 
388  *mediaptr = 4;
389  if ( want_atapi )
390  {
391  VERBOSE_KPRINTF(1, "Ps2 Drive Spindle -> Atapi \n");
392  retres = 1;
393  for ( i = 0; i < 10 && retres && retres != -550; i += 1 )
394  {
395  memset(pkt, 0, sizeof(pkt));
396  pkt[0] = 0x1B;
397  pkt[4] = 3;
398  pkt[5] = 0;
399  retres = sceCdAtapiExecCmd(0, 0, 0, 0, pkt, sizeof(pkt), 1);
400  if ( retres )
401  continue;
402  retres = sceCdAtapiWaitResult_local();
403  if ( retres )
404  {
405  VERBOSE_KPRINTF(1, "Atapi Drive Spindle Start NG %d\n", i);
406  DelayThread(10000);
407  continue;
408  }
409  VERBOSE_KPRINTF(1, "Atapi Drive Spindle Start OK\n");
410  }
411  return retres;
412  }
413  VERBOSE_KPRINTF(1, "Atapi Drive Spindle -> Ps2\n");
414  tryres1 = 1;
415  for ( i = 0; i < 16 && tryres1 && tryres1 != -550; i += 1 )
416  {
417  memset(pkt, 0, sizeof(pkt));
418  pkt[0] = 0xF6;
419  pkt[2] = 0xA0;
420  pkt[8] = 6;
421  tryres1 = sceCdAtapiExecCmd_local(0, outbuf1, 1, sizeof(outbuf1), pkt, sizeof(pkt), 2);
422  if ( tryres1 )
423  continue;
424  tryres1 = sceCdAtapiWaitResult_local();
425  if ( tryres1 )
426  {
427  VERBOSE_KPRINTF(1, "Atapi Drive ATAPI_CMD_READ_EXT_INFO NG\n");
428  DelayThread(10000);
429  }
430  }
431  if ( !tryres1 )
432  {
433  int maskchk;
434 
435  maskchk = (((u8)outbuf1[5] >> 1) ^ 1) & 1;
436  if ( (outbuf1[3] & 0x10) )
437  {
438  char outbuf[8];
439 
440  VERBOSE_KPRINTF(1, "Atapi Drive Media found.\n");
441  memset(pkt, 0, sizeof(pkt));
442  pkt[0] = 0xF6;
443  pkt[2] = 0xA2;
444  pkt[8] = sizeof(outbuf);
445  if (
446  !sceCdAtapiExecCmd_local(0, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2) && !sceCdAtapiWaitResult_local() )
447  {
448  VERBOSE_KPRINTF(1, "Atapi Drive Media DVD:%d.\n", outbuf[5] & 0x20);
449  *mediaptr = (outbuf[5] & 0x20) ? 3 : 2;
450  }
451  }
452  else
453  {
454  VERBOSE_KPRINTF(1, "Atapi Drive No Media or Now checking.\n");
455  VERBOSE_KPRINTF(1, "Atapi Drive No Media or No SpinUp.\n");
456  *mediaptr = 4;
457  }
458  if ( maskchk )
459  {
460  VERBOSE_KPRINTF(1, "Atapi Drive Spin Up.\n");
461  retres = 1;
462  for ( i = 0; i < 16 && retres && retres != -550; i += 1 )
463  {
464  memset(pkt, 0, sizeof(pkt));
465  pkt[0] = 0x1B;
466  pkt[5] = 0;
467  retres = sceCdAtapiExecCmd(0, 0, 0, 0, pkt, sizeof(pkt), 1);
468  if ( retres )
469  continue;
470  retres = sceCdAtapiWaitResult_local();
471  if ( retres )
472  {
473  VERBOSE_KPRINTF(1, "Atapi Drive Spindle Stop NG\n");
474  DelayThread(10000);
475  continue;
476  }
477  VERBOSE_KPRINTF(1, "Atapi Drive Spindle Stop OK\n");
478  }
479  return retres;
480  }
481  VERBOSE_KPRINTF(1, "Atapi Drive Not Spin Up.\n");
482  retres = 1;
483  for ( i = 0; i < 16 && retres && retres != -550; i += 1 )
484  {
485  memset(pkt, 0, sizeof(pkt));
486  pkt[0] = 0x1B;
487  pkt[4] = 2;
488  pkt[5] = 0;
489  retres = sceCdAtapiExecCmd(0, 0, 0, 0, pkt, sizeof(pkt), 1);
490  if ( retres )
491  continue;
492  retres = sceCdAtapiWaitResult_local();
493  if ( retres )
494  {
495  VERBOSE_KPRINTF(1, "Atapi Drive EJECT NG\n");
496  DelayThread(10000);
497  continue;
498  }
499  VERBOSE_KPRINTF(1, "Atapi Drive EJECT OK\n");
500  *mediaptr = 256;
501  }
502  return retres;
503  }
504  return tryres1;
505 }
506 
507 static int sceCdAtapi_SC(void)
508 {
509  int i;
510  int retres;
511  char pkt[12];
512 
513  memset(pkt, 0, sizeof(pkt));
514  retres = 1;
515  pkt[0] = 0xF9;
516  pkt[2] = 0xB1;
517  pkt[8] = 0;
518  for ( i = 0; i < 10 && retres; i += 1 )
519  {
520  retres = sceCdAtapiExecCmd_local(0, 0, 0, 0, pkt, sizeof(pkt), 1);
521  if ( retres || (retres = sceCdAtapiWaitResult_local()) )
522  DelayThread(10000);
523  }
524  if ( retres )
525  {
526  VERBOSE_KPRINTF(1, "sceCdAtapi SC fail\n");
527  return retres;
528  }
529  *g_cd_sc_ffffffd9_ptr = 0;
530  VERBOSE_KPRINTF(1, "sceCdAtapi SC OK\n");
531  return 0;
532 }
533 
534 int xatapi_15_exec_f6_f9_scsi(void)
535 {
536  int i;
537  int retres1;
538  int retres2;
539  char pkt[12];
540  char outbuf[6];
541 
542  memset(pkt, 0, sizeof(pkt));
543  retres1 = 1;
544  pkt[0] = 0xF6;
545  pkt[2] = 0xB1;
546  pkt[8] = 6;
547  for ( i = 0; i < 4 && retres1; i += 1 )
548  {
549  retres1 = sceCdAtapiExecCmd_local(0, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2);
550  if ( retres1 || (retres1 = sceCdAtapiWaitResult_local()) )
551  DelayThread(10000);
552  }
553  if ( retres1 && !(outbuf[4] & 0x80) )
554  return retres1;
555  memset(pkt, 0, sizeof(pkt));
556  retres2 = 1;
557  pkt[0] = 0xF9;
558  pkt[2] = 0xB2;
559  pkt[8] = 0;
560  for ( i = 0; i < 10 && retres2; i += 1 )
561  {
562  retres2 = sceCdAtapiExecCmd_local(0, 0, 0, 0, pkt, sizeof(pkt), 1);
563  if ( !retres2 )
564  {
565  retres2 = sceCdAtapiWaitResult_local();
566  if ( !retres2 )
567  continue;
568  }
569  DelayThread(10000);
570  }
571  return retres2;
572 }
573 
574 static int sceCdAtapi_BC(void)
575 {
576  int i;
577  int retres1;
578  int retres4;
579  char pkt[12];
580  iop_event_info_t efinfo;
581  u32 waresontmp;
582  u32 efbits;
583  char outbuf1[6];
584  {
585  memset(pkt, 0, sizeof(pkt));
586  retres1 = 1;
587  pkt[0] = 0xF6;
588  pkt[2] = 0xB1;
589  pkt[8] = sizeof(outbuf1);
590  for ( i = 0; i < 10 && retres1; i += 1 )
591  {
592  retres1 = sceCdAtapiExecCmd_local(0, outbuf1, 1, sizeof(outbuf1), pkt, sizeof(pkt), 2);
593  if ( retres1 || (retres1 = sceCdAtapiWaitResult_local()) )
594  DelayThread(10000);
595  }
596  }
597  if ( !retres1 || (outbuf1[4] & 0x80) )
598  {
599  int retres2;
600 
601  memset(pkt, 0, sizeof(pkt));
602  retres2 = 1;
603  pkt[0] = 0xF9;
604  pkt[2] = 0xB2;
605  pkt[8] = 0;
606  for ( i = 0; i < 10 && retres2; i += 1 )
607  {
608  retres2 = sceCdAtapiExecCmd_local(0, 0, 0, 0, pkt, sizeof(pkt), 1);
609  if ( !retres2 )
610  {
611  retres2 = sceCdAtapiWaitResult_local();
612  if ( !retres2 )
613  continue;
614  }
615  DelayThread(10000);
616  }
617  }
618  {
619  int retres3;
620  char outbuf[6];
621 
622  memset(pkt, 0, sizeof(pkt));
623  retres3 = 1;
624  pkt[0] = 0xF6;
625  pkt[2] = 0xB1;
626  pkt[8] = sizeof(outbuf);
627  for ( i = 0; i < 10 && retres3; i += 1 )
628  {
629  retres3 = sceCdAtapiExecCmd_local(0, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2);
630  if ( retres3 || (retres3 = sceCdAtapiWaitResult_local()) )
631  DelayThread(10000);
632  }
633  if ( !retres3 && (outbuf[4] & 0x81) )
634  {
635  *g_cd_sc_ffffffd9_ptr = 1;
636  return 1;
637  }
638  }
639  {
640  char outbuf[16];
641 
642  memset(pkt, 0, sizeof(pkt));
643  retres4 = 1;
644  pkt[0] = 0xF6;
645  pkt[2] = 0xB0;
646  pkt[8] = sizeof(outbuf);
647  for ( i = 0; i < 10 && retres4; i += 1 )
648  {
649  retres4 = sceCdAtapiExecCmd_local(0, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2);
650  if ( retres4 || (retres4 = sceCdAtapiWaitResult_local()) )
651  DelayThread(10000);
652  }
653  if ( retres4 )
654  {
655  VERBOSE_KPRINTF(1, "sceCdAtapi BC 0 fail\n");
656  }
657  else
658  {
659  int flg;
660 
661  if ( g_should_wait_for_dma_flag && !ReferEventFlagStatus(g_adma_evfid, &efinfo) && !efinfo.currBits )
662  SetEventFlag(g_adma_evfid, 1);
663  SetEventFlag(g_acmd_evfid, 1);
664  retres4 = 0;
665  for ( i = 0; i < 100 && !retres4; i += 1 )
666  {
667  retres4 = cdvdman_167_atapi2dragon((u8 *)outbuf, &waresontmp);
668  if ( !retres4 || waresontmp )
669  DelayThread(10000);
670  }
671  flg = 0;
672  if ( !retres4 )
673  {
674  VERBOSE_KPRINTF(0, "sceCdAtapi BC 1 fail\n");
675  }
676  else
677  {
678  DelayThread(10000);
679  retres4 = 0;
680  for ( i = 0; i < 100 && !retres4; i += 1 )
681  {
682  retres4 = cdvdman_169_dragon2atapi((u8 *)outbuf, &waresontmp);
683  if ( !retres4 || waresontmp )
684  DelayThread(10000);
685  }
686  if ( !retres4 )
687  {
688  VERBOSE_KPRINTF(0, "sceCdAtapi BC 2 fail\n");
689  }
690  else
691  {
692  if ( g_should_wait_for_dma_flag )
693  WaitEventFlag(g_adma_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
694  retres4 = 1;
695  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
696  memset(pkt, 0, sizeof(pkt));
697  pkt[0] = 0xF9;
698  pkt[2] = 0xB0;
699  pkt[8] = sizeof(outbuf);
700  for ( i = 0; i < 10 && retres4; i += 1 )
701  {
702  retres4 = sceCdAtapiExecCmd_local(0, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 3);
703  if ( retres4 || (retres4 = sceCdAtapiWaitResult_local()) )
704  DelayThread(10000);
705  }
706  if ( retres4 )
707  {
708  VERBOSE_KPRINTF(1, "sceCdAtapi BC 3 fail\n");
709  }
710  else
711  {
712  VERBOSE_KPRINTF(1, "sceCdAtapi BC OK\n");
713  }
714  flg = 1;
715  }
716  }
717  if ( !flg )
718  {
719  if ( g_should_wait_for_dma_flag )
720  WaitEventFlag(g_adma_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
721  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
722  }
723  }
724  }
725  {
726  char outbuf[6];
727  int retres5;
728 
729  memset(pkt, 0, sizeof(pkt));
730  retres5 = 1;
731  pkt[0] = 0xF6;
732  pkt[2] = 0xB1;
733  pkt[8] = sizeof(outbuf);
734  for ( i = 0; i < 10 && retres5; i += 1 )
735  {
736  retres5 = sceCdAtapiExecCmd_local(0, outbuf, 1, sizeof(outbuf), pkt, sizeof(pkt), 2);
737  if ( retres5 || (retres5 = sceCdAtapiWaitResult_local()) )
738  DelayThread(10000);
739  }
740  if ( retres5 )
741  return retres4;
742  *g_cd_sc_ffffffd9_ptr = (outbuf[4] & 0x81) ? 1 : 0;
743  }
744  return retres4;
745 }
746 
747 static int atapi_spin_status_get(int unused_arg1, void *buf)
748 {
749  int result;
750  char pkt[12];
751 
752  (void)unused_arg1;
753  memset(pkt, 0, sizeof(pkt));
754  pkt[0] = 0xF6;
755  pkt[2] = 0xA0;
756  pkt[8] = 6;
757  result = xatapi_7_sceCdAtapiExecCmd(0, buf, 1, 6, pkt, sizeof(pkt), 2);
758  return (!result) ? xatapi_8_sceCdAtapiWaitResult() : result;
759 }
760 
761 static int atapi_check_if_drive_ready(int check_nowait)
762 {
763  u8 ata_control;
764  int drive_err;
765  int unitreadyctrl;
766  int senseret;
767 
768  drive_err = 0;
769  VERBOSE_KPRINTF(1, "Atapi Drive Ready Call %d\n", check_nowait);
770  ata_control = xatapi_12_get_ata_control();
771  VERBOSE_KPRINTF(1, "Atapi Drive Ready %04x\n", ata_control);
772  if ( !check_nowait )
773  {
774  int req_test_unit_ready_tmp1;
775 
776  req_test_unit_ready_tmp1 = -1;
777  while ( req_test_unit_ready_tmp1 < 0 )
778  {
779  char spinstatus_tmp[6];
780 
781  while ( (ata_control & 0xC0) != 64 )
782  {
783  VERBOSE_KPRINTF(1, "Drive Not Ready %04x\n", ata_control);
784  DelayThread(2000);
785  ata_control = xatapi_12_get_ata_control();
786  }
787  req_test_unit_ready_tmp1 = do_atapi_request_test_unit_ready(0, &drive_err, &unitreadyctrl);
788  if ( req_test_unit_ready_tmp1 < 0 )
789  DelayThread(100000);
790  if ( !atapi_req_sense_get(0, &senseret) )
791  {
792  VERBOSE_KPRINTF(1, "ReqSense %08x\n", senseret);
793  if ( (senseret & 0xFFFFFF00) == 0x23A00 )
794  break;
795  }
796  if ( !atapi_spin_status_get(0, spinstatus_tmp) )
797  {
798  VERBOSE_KPRINTF(1, "Spin Status 3:%02x 5:%02x\n", (u8)spinstatus_tmp[3], (u8)spinstatus_tmp[5]);
799  if ( (spinstatus_tmp[3] & 2) || (spinstatus_tmp[3] & 0x80) )
800  break;
801  }
802  VERBOSE_KPRINTF(1, "Atapi Drive err %08x\n", drive_err);
803  }
804  return 2;
805  }
806  return ((ata_control & 0xC0) == 64 && do_atapi_request_test_unit_ready(0, &drive_err, &unitreadyctrl) >= 0
807  && !drive_err) ?
808  2 :
809  6;
810 }
811 
812 static int atapi_sceFsDevctlBlkIO(s16 dev_nr, void *buf, u32 lsn, u32 nsec, u32 secsize, sceFsRWTYPE rwtype)
813 {
814  u32 lsn_tmp;
815  u32 nsec_tmp;
816  int retres1;
817  int seccnt;
818  int i;
819  char pkt[12];
820 
821  lsn_tmp = lsn;
822  retres1 = 0;
823  VERBOSE_KPRINTF(1, "dma %c %08x, nsec %d\n", (rwtype == sceFsREADING) ? 'r' : 'w', lsn, nsec);
824  for ( nsec_tmp = nsec; !retres1 && nsec_tmp; nsec_tmp -= seccnt )
825  {
826  seccnt = (nsec_tmp >= 0x21) ? 32 : nsec_tmp;
827  for ( i = 3; i < 3; i += 1 )
828  {
829  xatapi_9_sceCdSpdAtaDmaStart((rwtype == sceFsREADING) ? 0 : 1);
830  memset(pkt, 0, sizeof(pkt));
831  pkt[0] = (rwtype == sceFsREADING) ? 0x28 : 0x2A;
832  pkt[2] = (lsn_tmp >> 24) & 0xFF;
833  pkt[3] = (lsn_tmp >> 16) & 0xFF;
834  pkt[4] = (lsn_tmp >> 8) & 0xFF;
835  pkt[5] = (lsn_tmp) & 0xFF;
836  pkt[8] = seccnt;
837  retres1 = xatapi_7_sceCdAtapiExecCmd(dev_nr, buf, seccnt, secsize, pkt, sizeof(pkt), 4);
838  if ( retres1 )
839  {
840  xatapi_10_sceCdSpdAtaDmaEnd();
841  break;
842  }
843  retres1 = xatapi_8_sceCdAtapiWaitResult();
844  xatapi_10_sceCdSpdAtaDmaEnd();
845  if ( retres1 != -510 )
846  {
847  break;
848  }
849  }
850  lsn_tmp += seccnt;
851  buf = (char *)buf + seccnt * secsize;
852  }
853  return retres1;
854 }
855 
856 static void expbay_device_reset(void)
857 {
858  if ( (*g_dev9_reg_power & 4) )
859  {
860  Kprintf("xatapi already Power On\n");
861  *g_dev9_reg_1460 |= 2;
862  return;
863  }
864  Kprintf("xatapi Power On Start\n");
865  *g_dev9_reg_power = (*g_dev9_reg_power & ~5) | 4;
866  DelayThread(500000);
867  *g_dev9_reg_1460 |= 2;
868  *g_dev9_reg_power |= 1;
869  DelayThread(500000);
870 }
871 
872 static int cd_atapi_intr_callback_cb(int cbarg)
873 {
874  VERBOSE_KPRINTF(1, "dev5 interrupt\n");
875  if ( p_dev5_intr_cb )
876  p_dev5_intr_cb(cbarg);
877  VERBOSE_KPRINTF(1, "dev5 interrupt end\n");
878  return 1;
879 }
880 
881 static void speedRegisterIntrDispatchCb(void *callback)
882 {
883  p_dev5_intr_cb = (int (*)(int flag))callback;
884 }
885 
886 static void sceDev5Init(void)
887 {
888  VERBOSE_KPRINTF(1, "dev5 atapi Init start\n");
889  sceCdSC(0xFFFFFFE5, (int *)cd_atapi_intr_callback_cb);
890  speed_device_init();
891  speed_init();
892  VERBOSE_KPRINTF(1, "dev5 atapi Init end\n");
893 }
894 
895 static int atapi_eject_interrupt_handler(int is_eject, void *userdata)
896 {
897  u32 buzzerres;
898 
899  (void)userdata;
900  if ( is_eject != 1 )
901  return 1;
902  VERBOSE_KPRINTF(1, "Eject intr : media removal\n");
903  return sceCdBuzzerCtl(&buzzerres);
904 }
905 
906 static int xatapi_do_init(void)
907 {
908  int (*oldcb)(int is_eject, void *userdata);
909  u32 *sc_tmp;
910  u32 trylocktmp;
911  u32 traylock_ret;
912 
913  if ( !create_event_flags() )
914  return 0;
915  sceCdSC(0xFFFFFFD9, (int *)&sc_tmp);
916  g_cd_sc_ffffffd9_ptr = sc_tmp;
917  sceCdSC(0xFFFFFFD7, (int *)&sc_tmp);
918  g_bf40200a_is_set_ptr = (int)sc_tmp;
919  oldcb = (int (*)(int is_eject, void *userdata))sceCdSetAtapiEjectCallback(
920  (int (*)(int is_eject, void *userdata))atapi_eject_interrupt_handler, 0);
921  if ( !sceCdGetMediumRemoval(&trylocktmp, &traylock_ret) )
922  {
923  VERBOSE_KPRINTF(0, "xatapi:sceCdGetMediumRemoval NG(%x) !!\n", traylock_ret);
924  trylocktmp = 0;
925  }
926  if ( trylocktmp )
927  {
928  VERBOSE_KPRINTF(0, "xatapi:Tray locked !!\n");
929  }
930  else if ( sceCdSetMediumRemoval(1, &traylock_ret) )
931  {
932  VERBOSE_KPRINTF(0, "xatapi:Tray lock\n");
933  }
934  else
935  {
936  VERBOSE_KPRINTF(0, "xatapi:Tray lock NG(%x) !!\n", traylock_ret);
937  trylocktmp = 0;
938  }
939  expbay_device_reset();
940  VERBOSE_KPRINTF(0, "xatapi Dev5->Rainbow\n");
941  sceCdChgSys(1);
942  VERBOSE_KPRINTF(1, "xatapi Dev5->Rainbow end\n");
943  VERBOSE_KPRINTF(1, "sceDev5Init Call\n");
944  sceDev5Init();
945  VERBOSE_KPRINTF(1, "sceAtInterInit Call\n");
946  sceAtInterInit();
947  VERBOSE_KPRINTF(1, "sceAtapiInit Call\n");
948  sceAtapiInit(0);
949  VERBOSE_KPRINTF(1, "sceAtapiInit end\n");
950  sceCdSC(0xFFFFFFE1, (int *)chgsys_callback_cb);
951  DelayThread(10000);
952  if ( !trylocktmp )
953  {
954  if ( !sceCdSetMediumRemoval(0, &traylock_ret) )
955  {
956  VERBOSE_KPRINTF(0, "xatapi:Tray unlock NG(%x) !!\n", traylock_ret);
957  trylocktmp = 0;
958  }
959  else
960  {
961  VERBOSE_KPRINTF(0, "xatapi:Tray unlock\n");
962  }
963  }
964  sceCdSetAtapiEjectCallback(oldcb, 0);
965  return 1;
966 }
967 
968 int xatapi_2_terminate(int with_quit)
969 {
970  int sc_tmp;
971 
972  (void)with_quit;
973  sc_tmp = 0;
974  sceCdSC(0xFFFFFFE1, &sc_tmp);
975  sceCdSC(0xFFFFFFE5, &sc_tmp);
976  sceCdSC(0xFFFFFFE0, &sc_tmp);
977  sceCdSC(0xFFFFFFDF, &sc_tmp);
978  sceCdSC(0xFFFFFFE4, &sc_tmp);
979  Kprintf("libxatapi_terminate\n");
980  return 0;
981 }
982 
983 static int xatapi_dev_devctl(
984  const iop_file_t *f, const char *name, int cmd, void *args, unsigned int arglen, void *buf, unsigned int buflen)
985 {
986  int retres1;
987  u32 efbits;
988 
989  (void)name;
990  retres1 = 0;
991  VERBOSE_KPRINTF(1, "xatapi devctl: cmd:%08x arg:%d\n", cmd, *(u32 *)args);
992  if ( cmd == 0x439B && PollEventFlag(g_io_event_flag, 1, WEF_AND, &efbits) == KE_EVF_COND && *(u32 *)args == 1 )
993  {
994  *(u32 *)buf = 6;
995  return 0;
996  }
997  WaitEventFlag(g_io_event_flag, 1, WEF_AND | WEF_CLEAR, &efbits);
998  if ( g_devctl_retonly_unset )
999  {
1000  SetEventFlag(g_io_event_flag, 1);
1001  return -EIO;
1002  }
1003  switch ( cmd )
1004  {
1005  case 0x4332:
1006  retres1 = -EINVAL;
1007  if ( *(u32 *)args )
1008  {
1009  switch ( *((u32 *)args + 1) )
1010  {
1011  case 2:
1012  case 5:
1013  if ( !buflen )
1014  {
1015  retres1 = -EINVAL;
1016  break;
1017  }
1018  retres1 =
1019  xatapi_7_sceCdAtapiExecCmd(f->unit, buf, 1, buflen, (char *)args + 8, *(u32 *)args, *((u32 *)args + 1));
1020  break;
1021  case 3:
1022  case 6:
1023  if ( *((u32 *)args + 250) )
1024  {
1025  retres1 = xatapi_7_sceCdAtapiExecCmd(
1026  f->unit,
1027  (char *)args + 40,
1028  1,
1029  *((u32 *)args + 250),
1030  (char *)args + 8,
1031  *(u32 *)args,
1032  *((u32 *)args + 1));
1033  }
1034  else
1035  {
1036  retres1 = -EINVAL;
1037  }
1038  break;
1039  default:
1040  retres1 = xatapi_7_sceCdAtapiExecCmd(f->unit, 0, 0, 0, (char *)args + 8, *(u32 *)args, *((u32 *)args + 1));
1041  break;
1042  }
1043  if ( !retres1 )
1044  retres1 = xatapi_8_sceCdAtapiWaitResult();
1045  }
1046  break;
1047  case 0x4333:
1048  *(u32 *)buf = (u8)xatapi_11_sceAtaGetError();
1049  break;
1050  case 0x4334:
1051  *(u32 *)buf = (u8)xatapi_12_get_ata_control();
1052  break;
1053  case 0x4335:
1054  retres1 = sceCdAtapi_BC();
1055  if ( retres1 == 1 )
1056  retres1 = 0;
1057  break;
1058  case 0x4336:
1059  retres1 = sceCdAtapi_SC();
1060  break;
1061  case 0x4337: //?
1062  g_verbose_level = *(u32 *)args;
1063  break;
1064  case 0x4338:
1065  g_reset_scrambling_pack = *(u32 *)args;
1066  if ( g_reset_scrambling_pack )
1067  {
1068  g_pes_scrambling_control_pack = 0;
1069  }
1070  else
1071  {
1072  VERBOSE_KPRINTF(1, "pes scrambling control pack = %d\n", g_pes_scrambling_control_pack);
1073  }
1074  break;
1075  case 0x4339:
1076  DmaRun_spck((char *)args, arglen);
1077  break;
1078  case 0x433A:
1079  g_dma_mode_value = (*(u32 *)args & 0x40) ? 1 : 0;
1080  g_dma_speed_value = *(u32 *)args & 7;
1081  atapi_device_set_transfer_mode_outer(0);
1082  break;
1083  case 0x433B:
1084  if ( buf && buflen >= 2 )
1085  *(u16 *)buf = FpgaGetRevision();
1086  else
1087  Kprintf("CDIOC_ATAPI_GETFPGAREV:buffer NG\n");
1088  break;
1089  case 0x433C:
1090  if ( buf && buflen >= 4 )
1091  *(u32 *)buf = 0x4121300;
1092  else
1093  Kprintf("CDIOC_ATAPI_VERSION:buffer NG\n");
1094  break;
1095  case 0x433D:
1096  if ( buf && buflen >= 4 )
1097  *(u32 *)buf = g_pes_scrambling_control_pack;
1098  else
1099  Kprintf("CDIOC_ATAPI_GETPSCNT:buffer NG\n");
1100  break;
1101  case 0x439B:
1102  *(u32 *)buf = atapi_check_if_drive_ready(*(u32 *)args);
1103  break;
1104  case FDIOC_BLKIO:
1105  {
1106  sceFsDevctlBlkIO *bio_param;
1107  bio_param = (sceFsDevctlBlkIO *)args;
1108  if ( bio_param->blksiz != 2048 )
1109  {
1110  retres1 = -EINVAL;
1111  break;
1112  }
1113  VERBOSE_KPRINTF(
1114  1,
1115  "sceFsDevctlBlkIO Lsn:%d nsec:%d buffer:%08x Type:%d\n",
1116  bio_param->lbn,
1117  bio_param->nblk,
1118  bio_param->addr,
1119  bio_param->type);
1120  retres1 =
1121  atapi_sceFsDevctlBlkIO(f->unit, bio_param->addr, bio_param->lbn, bio_param->nblk, bio_param->blksiz, bio_param->type);
1122  }
1123 
1124  break;
1125  default:
1126  Kprintf("Un-support devctl %08x\n", cmd);
1127  retres1 = -EIO;
1128  break;
1129  }
1130  SetEventFlag(g_io_event_flag, 1);
1131  VERBOSE_KPRINTF(1, "xatapi devctl: cmd:%08x End.\n", cmd);
1132  return retres1;
1133 }
1134 
1135 int _start(int ac, char **av)
1136 {
1137  (void)ac;
1138  (void)av;
1139 
1140  Kprintf("xatapi_init Call\n");
1141  // Unofficial: initialize variable here
1142  g_dma_mode_value = 1;
1143  // Unofficial: initialize variable here
1144  g_dma_speed_value = 2;
1145  if ( RegisterLibraryEntries(&_exp_xatapi) )
1146  return MODULE_NO_RESIDENT_END;
1147  DelDrv("xatapi");
1148  if ( AddDrv(&ata_ioman_device) )
1149  {
1150  // Unofficial: omitted call to empty dev deinit function
1151  return MODULE_NO_RESIDENT_END;
1152  }
1153  return !xatapi_do_init() ? MODULE_NO_RESIDENT_END : MODULE_RESIDENT_END;
1154 }
1155 
1156 static int expbay_get_has_power(void)
1157 {
1158  return *g_dev9_reg_power & 4;
1159 }
1160 
1161 static void speedRegisterIntrCb(int intr, void *cb)
1162 {
1163  g_dev5_intr_cbs[intr] = cb;
1164 }
1165 
1166 static void speedRegisterPreDmaCb(int ctrl, void *cb)
1167 {
1168  g_dev5_predma_cbs[ctrl] = cb;
1169 }
1170 
1171 static void speedRegisterPostDmaCb(int ctrl, void *cb)
1172 {
1173  g_dev5_postdma_cbs[ctrl] = cb;
1174 }
1175 
1176 static int speed_intr_dispatch(int flag)
1177 {
1178  int i;
1179  int j;
1180  USE_DEV5_SPEED_REGS();
1181 
1182  if ( flag == 1 )
1183  {
1184  AtaEjectIntrHandle();
1185  return 0;
1186  }
1187  if ( (dev5_speed_regs->r_spd_intr_stat & 0x3EFC) )
1188  {
1189  VERBOSE_KPRINTF(
1190  0, "SL3 register access failed(%x:%x) !!\n", dev5_speed_regs->r_spd_intr_stat, dev5_speed_regs->r_spd_intr_mask);
1191  return 0;
1192  }
1193  for ( i = 0; i < 3 && (u16)(dev5_speed_regs->r_spd_intr_stat & dev5_speed_regs->r_spd_intr_mask); i += 1 )
1194  {
1195  for ( j = 0; j < (int)(sizeof(g_dev5_intr_cbs) / sizeof(g_dev5_intr_cbs[0])); j += 1 )
1196  {
1197  if (
1198  g_dev5_intr_cbs[j]
1199  && (((int)(u16)(dev5_speed_regs->r_spd_intr_stat & dev5_speed_regs->r_spd_intr_mask) >> j) & 1) )
1200  g_dev5_intr_cbs[j](flag);
1201  }
1202  }
1203  return 0;
1204 }
1205 
1206 static void speedIntrEnable(s16 mask)
1207 {
1208  int state;
1209  USE_DEV5_SPEED_REGS();
1210 
1211  CpuSuspendIntr(&state);
1212  dev5_speed_regs->r_spd_intr_mask &= ~mask;
1213  dev5_speed_regs->r_spd_intr_mask |= mask;
1214  CpuResumeIntr(state);
1215 }
1216 
1217 static void speedIntrDisable(s16 mask)
1218 {
1219  int state;
1220  USE_DEV5_SPEED_REGS();
1221 
1222  CpuSuspendIntr(&state);
1223  dev5_speed_regs->r_spd_intr_mask &= ~mask;
1224  CpuResumeIntr(state);
1225 }
1226 
1227 static int SpdDmaTransfer(unsigned int device, void *buf, u32 bcr_in, int dir)
1228 {
1229  int result;
1230  USE_DEV5_SPEED_REGS();
1231 
1232  dmac_ch_set_chcr(IOP_DMAC_CDVD, 0);
1233  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1234  if ( device >= 2 && (!g_dev5_predma_cbs[device] || !g_dev5_postdma_cbs[device]) )
1235  return -1;
1236  VERBOSE_KPRINTF(1, "Wait Intr\n");
1237  result = WaitSema(g_dma_lock_sema);
1238  if ( result < 0 )
1239  return result;
1240  dev5_speed_regs->r_spd_dma_ctrl = (dev5_speed_regs->r_spd_rev_1 >= 0x11) ? ((device & 1) | 6) : ((device & 3) | 4);
1241  if ( g_dev5_predma_cbs[device] )
1242  g_dev5_predma_cbs[device](bcr_in, dir);
1243  VERBOSE_KPRINTF(1, "DMA Ch3 Set.\n");
1244  VERBOSE_KPRINTF(1, "Set MADR3:%08x Set BCR3:%08x\n", buf, bcr_in);
1245  dmac_ch_set_madr(IOP_DMAC_CDVD, (u32)buf);
1246  dmac_ch_set_bcr(IOP_DMAC_CDVD, bcr_in);
1247  dmac_ch_set_chcr(IOP_DMAC_CDVD, dir | 0x41000200);
1248  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1249  VERBOSE_KPRINTF(
1250  1,
1251  "CHCR3:%08x MADR3:%08x BCR3:%08x\n",
1252  dmac_ch_get_chcr(IOP_DMAC_CDVD),
1253  dmac_ch_get_madr(IOP_DMAC_CDVD),
1254  dmac_ch_get_bcr(IOP_DMAC_CDVD));
1255  while ( (dmac_ch_get_chcr(IOP_DMAC_CDVD) & 0x1000000) )
1256  {
1257  }
1258  VERBOSE_KPRINTF(1, "MADR3= %08x\n", dmac_ch_get_madr(IOP_DMAC_CDVD));
1259  if ( g_dev5_postdma_cbs[device] )
1260  g_dev5_postdma_cbs[device](bcr_in, dir);
1261  VERBOSE_KPRINTF(1, "SpdDmaTransfer End.\n");
1262  SignalSema(g_dma_lock_sema);
1263  return 0;
1264 }
1265 
1266 static int SpdDmaTransfer_extrans_1(unsigned int device, void *buf, u32 bcr_in, int dir)
1267 {
1268  int result;
1269  USE_DEV5_SPEED_REGS();
1270 
1271  dmac_ch_set_chcr(IOP_DMAC_CDVD, 0);
1272  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1273  if ( device >= 2 && (!g_dev5_predma_cbs[device] || !g_dev5_postdma_cbs[device]) )
1274  return -1;
1275  VERBOSE_KPRINTF(1, "Wait Intr\n");
1276  result = WaitSema(g_dma_lock_sema);
1277  if ( result < 0 )
1278  return result;
1279  dev5_speed_regs->r_spd_dma_ctrl = (dev5_speed_regs->r_spd_rev_1 >= 0x11) ? ((device & 1) | 6) : ((device & 3) | 4);
1280  if ( g_dev5_predma_cbs[device] )
1281  g_dev5_predma_cbs[device](bcr_in, dir);
1282  speedIntrDisable(256);
1283  FpgaLayer1On();
1284  FpgaXfrenOn();
1285  VERBOSE_KPRINTF(1, "DMA Ch3 Set.\n");
1286  VERBOSE_KPRINTF(1, "Set MADR3:%08x Set BCR3:%08x\n", buf, bcr_in);
1287  dmac_ch_set_madr(IOP_DMAC_CDVD, (u32)buf);
1288  dmac_ch_set_bcr(IOP_DMAC_CDVD, bcr_in);
1289  dmac_ch_set_chcr(IOP_DMAC_CDVD, dir | 0x41000200);
1290  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1291  VERBOSE_KPRINTF(
1292  1,
1293  "CHCR3:%08x MADR3:%08x BCR3:%08x\n",
1294  dmac_ch_get_chcr(IOP_DMAC_CDVD),
1295  dmac_ch_get_madr(IOP_DMAC_CDVD),
1296  dmac_ch_get_bcr(IOP_DMAC_CDVD));
1297  while ( (dmac_ch_get_chcr(IOP_DMAC_CDVD) & 0x1000000) )
1298  {
1299  }
1300  VERBOSE_KPRINTF(1, "MADR3= %08x\n", dmac_ch_get_madr(IOP_DMAC_CDVD));
1301  FpgaCheckWriteBuffer();
1302  FpgaXfrenOff();
1303  FpgaLayer1Off();
1304  speedIntrEnable(256);
1305  if ( g_dev5_postdma_cbs[device] )
1306  g_dev5_postdma_cbs[device](bcr_in, dir);
1307  VERBOSE_KPRINTF(1, "SpdDmaTransfer_extrans End.\n");
1308  SignalSema(g_dma_lock_sema);
1309  return 0;
1310 }
1311 
1312 static int SpdDmaTransfer_extrans_2(unsigned int device, void *buf, u32 bcr_in, int dir)
1313 {
1314  int result;
1315 
1316  dmac_ch_set_chcr(IOP_DMAC_CDVD, 0);
1317  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1318  if ( device >= 2 && (!g_dev5_predma_cbs[device] || !g_dev5_postdma_cbs[device]) )
1319  return -1;
1320  VERBOSE_KPRINTF(1, "Wait Intr\n");
1321  result = WaitSema(g_dma_lock_sema);
1322  if ( result < 0 )
1323  return result;
1324  VERBOSE_KPRINTF(1, "DMA Ch3 Set.\n");
1325  VERBOSE_KPRINTF(1, "Set MADR3:%08x Set BCR3:%08x\n", buf, bcr_in);
1326  dmac_ch_set_madr(IOP_DMAC_CDVD, (u32)buf);
1327  dmac_ch_set_bcr(IOP_DMAC_CDVD, bcr_in);
1328  dmac_ch_set_chcr(IOP_DMAC_CDVD, dir | 0x41000200);
1329  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1330  VERBOSE_KPRINTF(
1331  1,
1332  "CHCR3:%08x MADR3:%08x BCR3:%08x\n",
1333  dmac_ch_get_chcr(IOP_DMAC_CDVD),
1334  dmac_ch_get_madr(IOP_DMAC_CDVD),
1335  dmac_ch_get_bcr(IOP_DMAC_CDVD));
1336  while ( (dmac_ch_get_chcr(IOP_DMAC_CDVD) & 0x1000000) )
1337  {
1338  }
1339  VERBOSE_KPRINTF(1, "MADR3= %08x\n", dmac_ch_get_madr(IOP_DMAC_CDVD));
1340  VERBOSE_KPRINTF(1, "SpdDmaTransfer_extrans End.\n");
1341  SignalSema(g_dma_lock_sema);
1342  return 0;
1343 }
1344 
1345 static int SpdDmaTransfer_extrans_3(unsigned int device, void *buf, u32 bcr_in, int dir)
1346 {
1347  int result;
1348 
1349  dmac_ch_set_chcr(IOP_DMAC_CDVD, 0);
1350  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1351  if ( device >= 2 && (!g_dev5_predma_cbs[device] || !g_dev5_postdma_cbs[device]) )
1352  return -1;
1353  VERBOSE_KPRINTF(1, "Wait Intr\n");
1354  result = WaitSema(g_dma_lock_sema);
1355  if ( result < 0 )
1356  return result;
1357  FpgaLayer1On();
1358  FpgaXfrenOn();
1359  VERBOSE_KPRINTF(1, "DMA Ch3 Set.\n");
1360  VERBOSE_KPRINTF(1, "Set MADR3:%08x Set BCR3:%08x\n", buf, bcr_in);
1361  dmac_ch_set_madr(IOP_DMAC_CDVD, (u32)buf);
1362  dmac_ch_set_bcr(IOP_DMAC_CDVD, bcr_in);
1363  dmac_ch_set_chcr(IOP_DMAC_CDVD, dir | 0x41000200);
1364  dmac_ch_get_chcr(IOP_DMAC_CDVD);
1365  VERBOSE_KPRINTF(
1366  1,
1367  "CHCR3:%08x MADR3:%08x BCR3:%08x\n",
1368  dmac_ch_get_chcr(IOP_DMAC_CDVD),
1369  dmac_ch_get_madr(IOP_DMAC_CDVD),
1370  dmac_ch_get_bcr(IOP_DMAC_CDVD));
1371  while ( (dmac_ch_get_chcr(IOP_DMAC_CDVD) & 0x1000000) )
1372  {
1373  }
1374  VERBOSE_KPRINTF(1, "MADR3= %08x\n", dmac_ch_get_madr(IOP_DMAC_CDVD));
1375  FpgaCheckWriteBuffer2();
1376  FpgaXfrenOff();
1377  FpgaLayer1Off();
1378  VERBOSE_KPRINTF(1, "SpdDmaTransfer_extrans End.\n");
1379  SignalSema(g_dma_lock_sema);
1380  return 0;
1381 }
1382 
1383 static void speedLEDCtl(int ctl)
1384 {
1385  USE_DEV5_SPEED_REGS();
1386 
1387  // Unofficial: was 8 bit access
1388  dev5_speed_regs->r_spd_pio_data = !ctl;
1389 }
1390 
1391 static void speed_init(void)
1392 {
1393  int i;
1394  iop_sema_t semaparam;
1395 
1396  semaparam.attr = SA_THPRI;
1397  semaparam.initial = 1;
1398  semaparam.max = 1;
1399  semaparam.option = 0;
1400  g_dma_lock_sema = CreateSema(&semaparam);
1401  if ( g_dma_lock_sema <= 0 )
1402  return;
1403  speedIntrDisable(0xFFFF);
1404  speedRegisterIntrDispatchCb(speed_intr_dispatch);
1405  for ( i = 0; i < (int)(sizeof(g_dev5_intr_cbs) / sizeof(g_dev5_intr_cbs[0])); i += 1 )
1406  {
1407  g_dev5_intr_cbs[i] = 0;
1408  }
1409  for ( i = 0; i < (int)(sizeof(g_dev5_predma_cbs) / sizeof(g_dev5_predma_cbs[0])); i += 1 )
1410  {
1411  g_dev5_predma_cbs[i] = 0;
1412  }
1413  for ( i = 0; i < (int)(sizeof(g_dev5_postdma_cbs) / sizeof(g_dev5_postdma_cbs[0])); i += 1 )
1414  {
1415  g_dev5_postdma_cbs[i] = 0;
1416  }
1417  speedLEDCtl(0);
1418  return;
1419 }
1420 
1421 static void speed_device_init(void)
1422 {
1423  int idx;
1424  const char *revtypes[4];
1425  USE_DEV5_SPEED_REGS();
1426 
1427  revtypes[0] = "unknown";
1428  revtypes[1] = "TS";
1429  revtypes[2] = "ES1";
1430  revtypes[3] = "ES2";
1431  switch ( dev5_speed_regs->r_spd_rev_1 )
1432  {
1433  case 9:
1434  idx = 1;
1435  break;
1436  case 16:
1437  idx = 2;
1438  break;
1439  case 17:
1440  idx = 3;
1441  break;
1442  default:
1443  idx = 0;
1444  break;
1445  }
1446  if ( idx )
1447  {
1448  VERBOSE_KPRINTF(1, "Speed chip: %s\n", revtypes[idx]);
1449  }
1450  else
1451  {
1452  VERBOSE_KPRINTF(1, "Speed chip: Rev %x\n", dev5_speed_regs->r_spd_rev_1);
1453  }
1454  VERBOSE_KPRINTF(
1455  1, "Speed version(rev3.rev8) = %04x.%04x\n", dev5_speed_regs->r_spd_rev_3, dev5_speed_regs->r_spd_rev_8);
1456 }
1457 
1458 static void do_hex_dump(void *ptr, int len)
1459 {
1460  int i;
1461  int charbuf_offs;
1462  int j;
1463  char charbuf[17];
1464 
1465  if ( !g_verbose_level )
1466  {
1467  return;
1468  }
1469  Kprintf("Hex dump 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f");
1470  j = 0;
1471  for ( i = 0; i < len; i += 256 )
1472  {
1473  for ( j = 0; j < (((len - i) > 256) ? 256 : (len - i)); j += 1 )
1474  {
1475  charbuf_offs = j & 0xF;
1476  if ( !charbuf_offs && j )
1477  {
1478  charbuf[16] = 0;
1479  Kprintf(" %s\n%08x", charbuf, i + j);
1480  }
1481  Kprintf(" %02x", (u8)((char *)ptr)[i + j]);
1482  charbuf[charbuf_offs] = (((char *)ptr)[i + j] >= 0 && isgraph(((char *)ptr)[i + j])) ? ((char *)ptr)[i + j] : '.';
1483  }
1484  }
1485  charbuf_offs = j & 0xF;
1486  for ( i = 0; (unsigned int)i < (unsigned int)((sizeof(charbuf) - 1) - charbuf_offs); i += 1 )
1487  {
1488  Kprintf("\t ");
1489  }
1490  charbuf[charbuf_offs] = 0;
1491  Kprintf("%s\n", charbuf);
1492 }
1493 
1494 static void ata_pre_dma_cb(void)
1495 {
1496  USE_DEV5_SPEED_REGS();
1497 
1498  VERBOSE_KPRINTF(1, "ata_pre_dma_handler:old %x\n", dev5_speed_regs->r_spd_xfr_ctrl);
1499  dev5_speed_regs->r_spd_xfr_ctrl |= 0x80;
1500  VERBOSE_KPRINTF(1, "ata_pre_dma_handler:new %x\n", dev5_speed_regs->r_spd_xfr_ctrl);
1501 }
1502 
1503 static void ata_post_dma_cb(void)
1504 {
1505  USE_DEV5_SPEED_REGS();
1506 
1507  VERBOSE_KPRINTF(1, "ata_post_dma_handler:old %x\n", dev5_speed_regs->r_spd_xfr_ctrl);
1508  dev5_speed_regs->r_spd_xfr_ctrl &= ~0x80;
1509  VERBOSE_KPRINTF(1, "ata_post_dma_handler:new %x\n", dev5_speed_regs->r_spd_xfr_ctrl);
1510 }
1511 
1512 static int vReferEventFlagStatus(int ef, iop_event_info_t *info)
1513 {
1514  return (QueryIntrContext()) ? iReferEventFlagStatus(ef, info) : ReferEventFlagStatus(ef, info);
1515 }
1516 
1517 void xatapi_9_sceCdSpdAtaDmaStart(int dir)
1518 {
1519  int spd_if_ctrl_manip_2;
1520  u32 efbits;
1521  USE_DEV5_SPEED_REGS();
1522 
1523  g_is_wait_busy = 0;
1524  WaitEventFlag(g_adma_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
1525  g_should_wait_for_dma_flag = 1;
1526  VERBOSE_KPRINTF(1, "sceCdSpdAtaDmaStart Call %d :Read 0:Write 1\n", dir);
1527  dev5_speed_regs->r_spd_dbuf_stat = 3;
1528  spd_if_ctrl_manip_2 = (dev5_speed_regs->r_spd_if_ctrl & 1) | (dir ? 0x4C : 0x4E);
1529  dev5_speed_regs->r_spd_if_ctrl = spd_if_ctrl_manip_2;
1530  VERBOSE_KPRINTF(1, "sceCdSpdAtaDmaStart Write R_IF_CTR:%x\n", spd_if_ctrl_manip_2);
1531  dev5_speed_regs->r_spd_xfr_ctrl = dir | 6;
1532  VERBOSE_KPRINTF(
1533  1,
1534  "sceCdSpdAtaDmaStart R_IF_CTR:%x R_XFR_CTRL:%x\n",
1535  dev5_speed_regs->r_spd_if_ctrl,
1536  dev5_speed_regs->r_spd_xfr_ctrl);
1537 }
1538 
1539 void xatapi_10_sceCdSpdAtaDmaEnd(void)
1540 {
1541  iop_event_info_t efinfo;
1542  USE_DEV5_SPEED_REGS();
1543 
1544  VERBOSE_KPRINTF(1, "sceCdSpdAtaDmaEnd Call\n");
1545  if ( !g_should_wait_for_dma_flag )
1546  {
1547  VERBOSE_KPRINTF(1, "sceCdSpdAtaDmaEnd No Start(flag)\n");
1548  return;
1549  }
1550  if ( vReferEventFlagStatus(g_adma_evfid, &efinfo) || (efinfo.currBits & 1) )
1551  {
1552  VERBOSE_KPRINTF(1, "sceCdSpdAtaDmaEnd No Start\n");
1553  g_should_wait_for_dma_flag = 0;
1554  return;
1555  }
1556  dev5_speed_regs->r_spd_xfr_ctrl = 1;
1557  dev5_speed_regs->r_spd_if_ctrl &= ~0x4;
1558  dev5_speed_regs->r_spd_dbuf_stat = 3;
1559  dev5_speed_regs->r_spd_if_ctrl &= ~0x84;
1560  dev5_speed_regs->r_spd_if_ctrl |= 0x80;
1561  dev5_speed_regs->r_spd_if_ctrl &= ~0x84;
1562  ata_pio_mode(0);
1563  if ( g_dma_mode_value )
1564  ata_ultra_dma_mode(g_dma_speed_value);
1565  else
1566  ata_multiword_dma_mode(g_dma_speed_value);
1567  g_should_wait_for_dma_flag = 0;
1568  SetEventFlag(g_adma_evfid, 1);
1569 }
1570 
1571 static void ata_pio_mode(int mode)
1572 {
1573  USE_DEV5_SPEED_REGS();
1574 
1575  VERBOSE_KPRINTF(1, "SpdAtaSetPioTiming %d\n", mode);
1576  switch ( mode )
1577  {
1578  case 0:
1579  default:
1580  dev5_speed_regs->r_spd_pio_mode = 146;
1581  break;
1582  case 1:
1583  dev5_speed_regs->r_spd_pio_mode = 114;
1584  break;
1585  case 2:
1586  dev5_speed_regs->r_spd_pio_mode = 50;
1587  break;
1588  case 3:
1589  dev5_speed_regs->r_spd_pio_mode = 36;
1590  break;
1591  case 4:
1592  dev5_speed_regs->r_spd_pio_mode = 35;
1593  break;
1594  }
1595 }
1596 
1597 static void ata_multiword_dma_mode(int mode)
1598 {
1599  USE_DEV5_SPEED_REGS();
1600 
1601  VERBOSE_KPRINTF(1, "SpdAtaSetMdmaTiming %d\n", mode);
1602  switch ( mode )
1603  {
1604  case 0:
1605  default:
1606  dev5_speed_regs->r_spd_mwdma_mode = 255;
1607  break;
1608  case 1:
1609  dev5_speed_regs->r_spd_mwdma_mode = 69;
1610  break;
1611  case 2:
1612  dev5_speed_regs->r_spd_mwdma_mode = 36;
1613  break;
1614  }
1615  dev5_speed_regs->r_spd_if_ctrl = (dev5_speed_regs->r_spd_if_ctrl & ~0x49) | 0x48;
1616 }
1617 
1618 static void ata_ultra_dma_mode(int mode)
1619 {
1620  USE_DEV5_SPEED_REGS();
1621 
1622  VERBOSE_KPRINTF(1, "SpdAtaSetUdmaTiming %d\n", mode);
1623  switch ( mode )
1624  {
1625  case 0:
1626  default:
1627  dev5_speed_regs->r_spd_udma_mode = 167;
1628  break;
1629  case 1:
1630  dev5_speed_regs->r_spd_udma_mode = 133;
1631  break;
1632  case 2:
1633  dev5_speed_regs->r_spd_udma_mode = 99;
1634  break;
1635  case 3:
1636  dev5_speed_regs->r_spd_udma_mode = 98;
1637  break;
1638  case 4:
1639  dev5_speed_regs->r_spd_udma_mode = 97;
1640  break;
1641  }
1642  dev5_speed_regs->r_spd_if_ctrl = dev5_speed_regs->r_spd_if_ctrl | 0x49;
1643 }
1644 
1645 static int ata_intr_cb(int flag)
1646 {
1647  VERBOSE_KPRINTF(1, "call AtaIntrHandle %d\n", flag);
1648  speedIntrDisable(3);
1649  iSetEventFlag(g_atapi_event_flag, 2);
1650  return 1;
1651 }
1652 
1653 static void AtaEjectIntrHandle(void)
1654 {
1655  VERBOSE_KPRINTF(1, "call AtaEjectIntrHandle\n");
1656  g_is_wait_busy = 1;
1657  iSetEventFlag(g_atapi_event_flag, 4);
1658 }
1659 
1660 static unsigned int AtaAlarmrHandle(void *usrdat)
1661 {
1662  (void)usrdat;
1663 
1664  VERBOSE_KPRINTF(1, "call AtaAlarmrHandle\n");
1665  iSetEventFlag(g_atapi_event_flag, 1);
1666  return 0;
1667 }
1668 
1669 int xatapi_14_set_speed_reg(int regaddr, u16 regval)
1670 {
1671  u32 efbits;
1672  USE_DEV5_SPEED_REGS();
1673 
1674  if ( (unsigned int)(regaddr - 64) < 0x1D )
1675  {
1676  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
1677  *(vu16 *)((char *)&dev5_speed_regs->unv00 + regaddr) = regval;
1678  SetEventFlag(g_acmd_evfid, 1);
1679  }
1680  return regval;
1681 }
1682 
1683 int xatapi_13_get_speed_reg(int regaddr)
1684 {
1685  int tmpval;
1686  u32 efbits;
1687  USE_DEV5_SPEED_REGS();
1688 
1689  if ( (unsigned int)(regaddr - 64) >= 0x1D )
1690  return 0;
1691  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
1692  tmpval = *(u16 *)((char *)&dev5_speed_regs->unv00 + regaddr);
1693  SetEventFlag(g_acmd_evfid, 1);
1694  return tmpval;
1695 }
1696 
1697 int xatapi_11_sceAtaGetError(void)
1698 {
1699  u8 r_spd_ata_error;
1700  u32 efbits;
1701  USE_DEV5_SPEED_REGS();
1702 
1703  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
1704  r_spd_ata_error = dev5_speed_regs->r_spd_ata_error;
1705  SetEventFlag(g_acmd_evfid, 1);
1706  return r_spd_ata_error;
1707 }
1708 
1709 int xatapi_12_get_ata_control(void)
1710 {
1711  u8 r_spd_ata_control;
1712  u32 efbits;
1713  USE_DEV5_SPEED_REGS();
1714 
1715  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
1716  r_spd_ata_control = dev5_speed_regs->r_spd_ata_control;
1717  SetEventFlag(g_acmd_evfid, 1);
1718  return r_spd_ata_control;
1719 }
1720 
1721 static int sceAtaGetError(void)
1722 {
1723  USE_DEV5_SPEED_REGS();
1724 
1725  return (u8)dev5_speed_regs->r_spd_ata_error;
1726 }
1727 
1728 static int ata_wait_busy1_busy(void)
1729 {
1730  unsigned int i;
1731  USE_DEV5_SPEED_REGS();
1732 
1733  for ( i = 0; i < 0x50; i += 1 )
1734  {
1735  if ( !(dev5_speed_regs->r_spd_ata_control & 0x80) )
1736  {
1737  return 0;
1738  }
1739  if ( !(u16)expbay_get_has_power() )
1740  {
1741  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busy, power off.\n");
1742  return -551;
1743  }
1744  if ( g_is_wait_busy )
1745  {
1746  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busy, tray eject.\n");
1747  return -550;
1748  }
1749  switch ( i / 0xA )
1750  {
1751  case 0:
1752  break;
1753  case 1:
1754  DelayThread(100);
1755  break;
1756  case 2:
1757  DelayThread(1000);
1758  break;
1759  case 3:
1760  DelayThread(10000);
1761  break;
1762  case 4:
1763  DelayThread(100000);
1764  break;
1765  default:
1766  DelayThread(1000000);
1767  break;
1768  }
1769  }
1770  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busy, timedout.\n", i / 0xA);
1771  return -502;
1772 }
1773 
1774 static int ata_wait_busy2_busy(void)
1775 {
1776  unsigned int i;
1777  USE_DEV5_SPEED_REGS();
1778 
1779  for ( i = 0; i < 55; i += 1 )
1780  {
1781  if ( !(dev5_speed_regs->r_spd_ata_control & 0x80) )
1782  {
1783  return 0;
1784  }
1785  if ( !(u16)expbay_get_has_power() )
1786  {
1787  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busy, power off.\n");
1788  return -551;
1789  }
1790  if ( g_is_wait_busy )
1791  {
1792  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busy, tray eject.\n");
1793  return -550;
1794  }
1795  switch ( i / 0xA )
1796  {
1797  case 0:
1798  break;
1799  case 1:
1800  DelayThread(100);
1801  break;
1802  case 2:
1803  DelayThread(1000);
1804  break;
1805  case 3:
1806  DelayThread(10000);
1807  break;
1808  case 4:
1809  DelayThread(100000);
1810  break;
1811  default:
1812  DelayThread(1000000);
1813  break;
1814  }
1815  }
1816  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busy, timedout.\n", i / 0xA);
1817  return -502;
1818 }
1819 
1820 static int ata_wait_bus_busy_busbusy(void)
1821 {
1822  unsigned int i;
1823  USE_DEV5_SPEED_REGS();
1824 
1825  for ( i = 0; i < 80; i += 1 )
1826  {
1827  if ( !(dev5_speed_regs->r_spd_ata_control & 0x88) )
1828  {
1829  return 0;
1830  }
1831  if ( !(u16)expbay_get_has_power() )
1832  {
1833  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busy, power off.\n");
1834  return -551;
1835  }
1836  if ( g_is_wait_busy )
1837  {
1838  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busbusy, tray eject.\n");
1839  return -550;
1840  }
1841  switch ( i / 0xA )
1842  {
1843  case 0:
1844  break;
1845  case 1:
1846  DelayThread(100);
1847  break;
1848  case 2:
1849  DelayThread(1000);
1850  break;
1851  case 3:
1852  DelayThread(10000);
1853  break;
1854  case 4:
1855  DelayThread(100000);
1856  break;
1857  default:
1858  DelayThread(1000000);
1859  break;
1860  }
1861  }
1862  VERBOSE_KPRINTF(1, "DEV5 ATA: error: wait busbusy, timedout.\n", i / 0xA);
1863  return -502;
1864 }
1865 
1866 static int ata_device_select(int device)
1867 {
1868  int result;
1869  USE_DEV5_SPEED_REGS();
1870 
1871  result = ata_wait_bus_busy_busbusy();
1872  if ( result < 0 )
1873  {
1874  return result;
1875  }
1876  if ( ((dev5_speed_regs->r_spd_ata_select >> 4) & 1) == device )
1877  {
1878  return 0;
1879  }
1880  dev5_speed_regs->r_spd_ata_select = (device ? 1 : 0) << 4;
1881  return ata_wait_bus_busy_busbusy();
1882 }
1883 
1884 static int sceAtaExecCmd(
1885  void *buf, u32 blkcount, u16 feature, u16 nsector, u16 sector, u16 lcyl, u16 hcyl, u16 select, u16 command, u32 unk10)
1886 {
1887  int result;
1888  int using_timeout;
1889  iop_sys_clock_t sysclk;
1890  USE_DEV5_SPEED_REGS();
1891 
1892  ClearEventFlag(g_atapi_event_flag, 0);
1893  g_is_wait_busy = 0;
1894  if ( !atad_devinfo[(select & 0x10) ? 1 : 0].exists )
1895  return -505;
1896  result = ata_device_select((select >> 4) & 1);
1897  if ( result )
1898  {
1899  return result;
1900  }
1901  if ( command == 142 || command == 176 )
1902  {
1903  VERBOSE_KPRINTF(1, "Not support Ata CMD\n");
1904  return -503;
1905  }
1906  atad_cmd_state.type = unk10;
1907  if ( !unk10 )
1908  return -506;
1909  atad_cmd_state.buf = buf;
1910  atad_cmd_state.blkcount = blkcount;
1911  if (
1912  !(dev5_speed_regs->r_spd_ata_control & 0x40)
1913  && ((command < 0x90 && command != 8) || (command >= 0xA2 || command < 0xA0)) )
1914  {
1915  VERBOSE_KPRINTF(1, "DEV5 ATA: error: device not ready\n");
1916  return -501;
1917  }
1918  switch ( atad_cmd_state.type )
1919  {
1920  case 1:
1921  case 8:
1922  using_timeout = 1;
1923  break;
1924  case 4:
1925  atad_cmd_state.dir = command != 0xC8;
1926  using_timeout = 1;
1927  break;
1928  case 5:
1929  case 6:
1930  using_timeout = 1;
1931  atad_cmd_state.dir = atad_cmd_state.type != 5;
1932  break;
1933  default:
1934  using_timeout = 0;
1935  break;
1936  }
1937  if ( atad_cmd_state.type != 9 )
1938  {
1939  if ( using_timeout )
1940  {
1941  USec2SysClock((command != 142 || feature != 244) ? 155000000 : 180000000, &sysclk);
1942  result = SetAlarm(&sysclk, AtaAlarmrHandle, 0);
1943  if ( result < 0 )
1944  return result;
1945  }
1946  if ( atad_cmd_state.type == 1 )
1947  speedIntrEnable(1);
1948  dev5_speed_regs->r_spd_ata_control = (!using_timeout) << 1;
1949  }
1950  dev5_speed_regs->r_spd_ata_error = feature;
1951  dev5_speed_regs->r_spd_ata_nsector = nsector;
1952  dev5_speed_regs->r_spd_ata_sector = sector;
1953  dev5_speed_regs->r_spd_ata_lcyl = lcyl;
1954  dev5_speed_regs->r_spd_ata_hcyl = hcyl;
1955  dev5_speed_regs->r_spd_ata_select = select | 0x40;
1956  dev5_speed_regs->r_spd_ata_status = command;
1957  speedLEDCtl(1);
1958  return 0;
1959 }
1960 
1961 int xatapi_5_sceAtaExecCmd(
1962  void *buf, u32 blkcount, u16 feature, u16 nsector, u16 sector, u16 lcyl, u16 hcyl, u16 select, u16 command, u32 unk10)
1963 {
1964  int retres;
1965  u32 efbits;
1966 
1967  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
1968  retres = sceAtaExecCmd(buf, blkcount, feature, nsector, sector, lcyl, hcyl, select, command, unk10);
1969  if ( retres )
1970  {
1971  SetEventFlag(g_acmd_evfid, 1);
1972  }
1973  return retres;
1974 }
1975 
1976 static int sceCdAtapiExecCmd_local(s16 n, void *buf, int nsec, int secsize, void *pkt, unsigned int pkt_len, int proto)
1977 {
1978  u16 feature_tmp;
1979  int result;
1980  int using_timeout;
1981  int retres1;
1982  char ata_status_1;
1983  unsigned int i;
1984  iop_sys_clock_t sysclk;
1985  USE_DEV5_SPEED_REGS();
1986 
1987  feature_tmp = 0;
1988  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd Start. pkt_len %d proto %d\n", pkt_len, proto);
1989  do_hex_dump(pkt, 12);
1990  g_is_wait_busy = 0;
1991  if ( !proto )
1992  return -506;
1993  atad_cmd_state.type_atapi = proto;
1994  atad_cmd_state.buf_atapi = buf;
1995  atad_cmd_state.blkcount_atapi = nsec;
1996  atad_cmd_state.blksize_atapi = secsize;
1997  switch ( proto )
1998  {
1999  case 1:
2000  case 8:
2001  using_timeout = 1;
2002  break;
2003  case 4:
2004  switch ( *(u8 *)pkt )
2005  {
2006  case 0x03:
2007  case 0x12:
2008  case 0x23:
2009  case 0x25:
2010  case 0x28:
2011  case 0x3C:
2012  case 0x46:
2013  case 0x4A:
2014  case 0x5A:
2015  case 0xA4:
2016  case 0xA8:
2017  case 0xB9:
2018  case 0xDA:
2019  atad_cmd_state.dir_atapi = 0;
2020  break;
2021  default:
2022  atad_cmd_state.dir_atapi = 1;
2023  break;
2024  }
2025  using_timeout = 1;
2026  feature_tmp = 1;
2027  break;
2028  case 5:
2029  case 6:
2030  using_timeout = 1;
2031  feature_tmp = 1;
2032  atad_cmd_state.dir_atapi = atad_cmd_state.type_atapi != 5;
2033  break;
2034  default:
2035  using_timeout = 0;
2036  break;
2037  }
2038  if (
2039  !g_reset_scrambling_pack && atad_cmd_state.type_atapi == 4 && atad_cmd_state.dir_atapi == 1
2040  && Mpeg2CheckScramble(
2041  (char *)atad_cmd_state.buf_atapi, atad_cmd_state.blkcount_atapi * atad_cmd_state.blksize_atapi) )
2042  {
2043  VERBOSE_KPRINTF(0, "illegal stream\n");
2044  return -560;
2045  }
2046  if ( using_timeout )
2047  {
2048  USec2SysClock(0x93D1CC0, &sysclk);
2049  result = SetAlarm(&sysclk, AtaAlarmrHandle, 0);
2050  if ( result < 0 )
2051  return result;
2052  }
2053  if ( atad_cmd_state.type_atapi == 1 )
2054  speedIntrEnable(1);
2055  dev5_speed_regs->r_spd_ata_control = (!using_timeout) << 1;
2056  result = sceAtaExecCmd(
2057  0,
2058  0,
2059  feature_tmp,
2060  0,
2061  0,
2062  (u8)((atad_cmd_state.blkcount_atapi & 0xFF) * (atad_cmd_state.blksize_atapi & 0xFF)),
2063  (u8)((u16)((atad_cmd_state.blkcount_atapi & 0xFFFF) * (atad_cmd_state.blksize_atapi & 0xFFFF)) >> 8),
2064  n << 4,
2065  0xA0,
2066  9);
2067  retres1 = result;
2068  if ( retres1 )
2069  {
2070  if ( using_timeout )
2071  {
2072  CancelAlarm(AtaAlarmrHandle, 0);
2073  }
2074  return retres1;
2075  }
2076  ata_status_1 = 0;
2077  while ( (ata_status_1 & 0x88) != 8 )
2078  {
2079  int ata_status_2;
2080 
2081  DelayThread(10000);
2082  ata_status_1 = dev5_speed_regs->r_spd_ata_status;
2083  ata_status_2 = dev5_speed_regs->r_spd_ata_status;
2084  VERBOSE_KPRINTF(1, "Status 0x%02x BSY %x DRQ %x\n", ata_status_2, ata_status_1 & 0x80, ata_status_1 & 8);
2085  if ( g_is_wait_busy )
2086  {
2087  if ( using_timeout )
2088  CancelAlarm(AtaAlarmrHandle, 0);
2089  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd Tray Eject while\n", ata_status_2);
2090  return -550;
2091  }
2092  if ( !(u16)expbay_get_has_power() )
2093  {
2094  if ( using_timeout )
2095  {
2096  CancelAlarm(AtaAlarmrHandle, 0);
2097  }
2098  return -551;
2099  }
2100  }
2101  if ( (ata_status_1 & 1) )
2102  {
2103  VERBOSE_KPRINTF(1, "iocmd err 0x%02x, 0x%02x\n", ata_status_1, sceAtaGetError());
2104  if ( using_timeout )
2105  {
2106  CancelAlarm(AtaAlarmrHandle, 0);
2107  }
2108  return -503;
2109  }
2110  if ( !(ata_status_1 & 8) )
2111  {
2112  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd_local ATA_NO_DREQ\n");
2113  }
2114  for ( i = 0; i < (pkt_len >> 1); i += 1 )
2115  {
2116  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd_local Packet %04x\n", ((u16 *)pkt)[i]);
2117  dev5_speed_regs->r_spd_ata_data = ((u16 *)pkt)[i];
2118  }
2119  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd End. cmd %02x\n", *(u8 *)pkt);
2120  if ( g_is_wait_busy )
2121  {
2122  if ( using_timeout )
2123  CancelAlarm(AtaAlarmrHandle, 0);
2124  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd Tray Eject last\n", pkt_len >> 1);
2125  return -550;
2126  }
2127  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd OK\n");
2128  return 0;
2129 }
2130 
2131 static int sceCdAtapiExecCmd(s16 n, void *buf, int nsec, int secsize, void *pkt, int pkt_len, int proto)
2132 {
2133  if ( pkt_len )
2134  {
2135  int pkt_scsi_cmd_2;
2136 
2137  pkt_scsi_cmd_2 = *(u8 *)pkt;
2138  VERBOSE_KPRINTF(1, "sceCdAtapiExecCmd %08x\n", pkt_scsi_cmd_2);
2139  if (
2140  (
2141  !(pkt_scsi_cmd_2 == 0x1B || pkt_scsi_cmd_2 == 0x12 || !pkt_scsi_cmd_2 || pkt_scsi_cmd_2 == 3
2142  || *g_cd_sc_ffffffd9_ptr))
2143  && !g_is_in_read_info && !sceCdAtapi_BC() )
2144  {
2145  ata_device_set_transfer_mode_outer(0);
2146  }
2147  }
2148  return sceCdAtapiExecCmd_local(n, buf, nsec, secsize, pkt, pkt_len, proto);
2149 }
2150 
2151 int xatapi_7_sceCdAtapiExecCmd(s16 n, void *buf, int nsec, int secsize, void *pkt, int pkt_len, int proto)
2152 {
2153  int retres;
2154  u32 efbits;
2155 
2156  WaitEventFlag(g_acmd_evfid, 1, WEF_AND | WEF_CLEAR, &efbits);
2157  retres = sceCdAtapiExecCmd(n, buf, nsec, secsize, pkt, pkt_len, proto);
2158  if ( retres )
2159  {
2160  SetEventFlag(g_acmd_evfid, 1);
2161  }
2162  return retres;
2163 }
2164 
2165 static int ata_pio_transfer(ata_cmd_state_t *cmd_state)
2166 {
2167  char r_spd_ata_status;
2168  USE_DEV5_SPEED_REGS();
2169 
2170  r_spd_ata_status = dev5_speed_regs->r_spd_ata_status;
2171  if ( (r_spd_ata_status & 1) )
2172  {
2173  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ATA PIO iocmd err 0x%02x, 0x%02x\n", r_spd_ata_status, sceAtaGetError());
2174  return -503;
2175  }
2176  else if ( (r_spd_ata_status & 8) )
2177  {
2178  int i;
2179 
2180  switch ( cmd_state->type )
2181  {
2182  case 2:
2183  {
2184  for ( i = 0; i < 256; i += 1 )
2185  {
2186  cmd_state->buf16[i] = dev5_speed_regs->r_spd_ata_data;
2187  }
2188  cmd_state->buf16 += 256;
2189  break;
2190  }
2191  case 3:
2192  {
2193  for ( i = 0; i < 256; i += 1 )
2194  {
2195  dev5_speed_regs->r_spd_ata_data = cmd_state->buf16[i];
2196  }
2197  cmd_state->buf16 += 256;
2198  break;
2199  }
2200  case 11:
2201  {
2202  for ( i = 0; i < 256; i += 1 )
2203  {
2204  dev5_speed_regs->r_spd_ata_data = cmd_state->buf16[i];
2205  }
2206  cmd_state->buf16 += 256;
2207  for ( i = 0; i < 4; i += 1 )
2208  {
2209  dev5_speed_regs->r_spd_ata_data = cmd_state->buf8[512 + i];
2210  }
2211  cmd_state->buf8 += 4;
2212  break;
2213  }
2214  default:
2215  break;
2216  }
2217  }
2218  else
2219  {
2220  return -504;
2221  }
2222  return 0;
2223 }
2224 
2225 static int IoRun_atapi(ata_cmd_state_t *cmd_state)
2226 {
2227  int result;
2228  u32 blktotal;
2229  unsigned int lhcyl;
2230  unsigned int i;
2231  USE_DEV5_SPEED_REGS();
2232 
2233  VERBOSE_KPRINTF(1, "Pio trans %d\n", cmd_state->blkcount_atapi * cmd_state->blksize_atapi);
2234  result = ata_wait_busy1_busy();
2235  if ( result < 0 )
2236  return result;
2237  result = 0;
2238  for ( blktotal = cmd_state->blkcount_atapi * cmd_state->blksize_atapi; result >= 0 && blktotal; blktotal -= lhcyl )
2239  {
2240  char r_spd_ata_status;
2241 
2242  r_spd_ata_status = dev5_speed_regs->r_spd_ata_status;
2243  if ( (r_spd_ata_status & 1) )
2244  {
2245  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ATAPI PIO iocmd err 0x%02x, 0x%02x\n", r_spd_ata_status, sceAtaGetError());
2246  return -503;
2247  }
2248  if ( !(r_spd_ata_status & 8) )
2249  return -504;
2250  // Unofficial: was 8 bit access
2251  lhcyl = (dev5_speed_regs->r_spd_ata_lcyl & 0xFF) | ((dev5_speed_regs->r_spd_ata_hcyl & 0xFF) << 8);
2252  VERBOSE_KPRINTF(1, "ByteCount Trans byte %04x\n", lhcyl);
2253  switch ( cmd_state->type_atapi )
2254  {
2255  case 2:
2256  {
2257  VERBOSE_KPRINTF(1, "IoRun_atapi input trans %d\n", cmd_state->blksize_atapi);
2258  for ( i = 0; i < (lhcyl >> 1); i += 1 )
2259  {
2260  ((u16 *)((char *)cmd_state->buf_atapi))[i] = dev5_speed_regs->r_spd_ata_data;
2261  }
2262  if ( (lhcyl & 1) )
2263  *((u8 *)cmd_state->buf_atapi + 2 * i) = dev5_speed_regs->r_spd_ata_data;
2264  cmd_state->buf_atapi = (char *)cmd_state->buf_atapi + lhcyl;
2265  break;
2266  }
2267  case 3:
2268  {
2269  VERBOSE_KPRINTF(1, "IoRun_atapi output trans %d\n", cmd_state->blksize_atapi);
2270  for ( i = 0; i < (lhcyl >> 1); i += 1 )
2271  {
2272  dev5_speed_regs->r_spd_ata_data = ((u16 *)cmd_state->buf_atapi)[i];
2273  }
2274  if ( (lhcyl & 1) )
2275  dev5_speed_regs->r_spd_ata_data = *((u8 *)cmd_state->buf_atapi + 2 * i);
2276  cmd_state->buf_atapi = (char *)cmd_state->buf_atapi + lhcyl;
2277  break;
2278  }
2279  default:
2280  break;
2281  }
2282  VERBOSE_KPRINTF(1, "IoRun_atapi trans End\n");
2283  result = ata_wait_busy1_busy();
2284  }
2285  return result;
2286 }
2287 
2288 static int atapi_transfer_wrapper(char *buf, unsigned int blkcount, int dir)
2289 {
2290  unsigned int blkcount_tmp;
2291  int i;
2292  unsigned int dbuf_stat_mask;
2293  int result;
2294  u8 Error;
2295  char spd_ata_status_tmp;
2296  u32 efbits;
2297  int flg;
2298  USE_DEV5_SPEED_REGS();
2299 
2300  for ( blkcount_tmp = blkcount; blkcount_tmp; blkcount_tmp -= (flg ? dbuf_stat_mask : 0) )
2301  {
2302  dbuf_stat_mask = 0;
2303  for ( i = 0; i < 20 && !dbuf_stat_mask; i += 1 )
2304  {
2305  dbuf_stat_mask = dev5_speed_regs->r_spd_dbuf_stat & 0x1F;
2306  }
2307  VERBOSE_KPRINTF(1, "*SPD_RINTR_STAT %02x\n", dev5_speed_regs->r_spd_intr_stat);
2308  VERBOSE_KPRINTF(1, "*R_DBUF_STAT %02x\n", dev5_speed_regs->r_spd_dbuf_stat);
2309  flg = 1;
2310  if ( !dbuf_stat_mask )
2311  {
2312  speedIntrEnable(3);
2313  VERBOSE_KPRINTF(1, "Wait Event\n");
2314  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2315  VERBOSE_KPRINTF(1, "Event come\n");
2316  if ( (efbits & 1) )
2317  {
2318  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun, ata timedout\n");
2319  return -502;
2320  }
2321  if ( (efbits & 4) )
2322  {
2323  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun, Media Eject\n");
2324  return -550;
2325  }
2326  if ( !(dev5_speed_regs->r_spd_intr_stat & 2) )
2327  {
2328  if ( (dev5_speed_regs->r_spd_ata_control & 1) )
2329  {
2330  spd_ata_status_tmp = dev5_speed_regs->r_spd_ata_status;
2331  Error = sceAtaGetError();
2332  VERBOSE_KPRINTF(1, "DEV5 ATA: error: cmd err 0x%02x, 0x%02x, while DmaRun\n", spd_ata_status_tmp, Error);
2333  return (!(Error & 0x80)) ? -503 : -510;
2334  }
2335  VERBOSE_KPRINTF(1, "DEV5 ATA: warning: ata intr without error.\n");
2336  flg = 0;
2337  }
2338  else
2339  {
2340  dbuf_stat_mask = dev5_speed_regs->r_spd_dbuf_stat & 0x1F;
2341  }
2342  }
2343  if ( flg )
2344  {
2345  if ( blkcount_tmp < dbuf_stat_mask )
2346  dbuf_stat_mask = blkcount_tmp;
2347  result = SpdDmaTransfer(0, buf, (dbuf_stat_mask << 18) | 0x20, dir);
2348  buf += dbuf_stat_mask << 9;
2349  if ( result < 0 )
2350  return result;
2351  }
2352  }
2353  return 0;
2354 }
2355 
2356 static int DmaRun_atapi(char *buf, int blkcount, int blksize, int dir)
2357 {
2358  unsigned int blkremainder;
2359  unsigned int blksectors;
2360  int i;
2361  unsigned int dbuf_stat_mask;
2362  int result;
2363  u8 Error;
2364  char spd_ata_status_tmp;
2365  unsigned int dbuf_stat_sectors;
2366  u32 efbits;
2367  USE_DEV5_SPEED_REGS();
2368 
2369  VERBOSE_KPRINTF(1, "DmaRun_atapi start\n");
2370  blkremainder = (blkcount * blksize) & 0x1FF;
2371  for ( blksectors = (unsigned int)(blkcount * blksize) >> 9; blksectors; blksectors -= dbuf_stat_mask )
2372  {
2373  dbuf_stat_mask = 0;
2374  for ( i = 0; i < 20 && !dbuf_stat_mask; i += 1 )
2375  {
2376  dbuf_stat_mask = dev5_speed_regs->r_spd_dbuf_stat & 0x1F;
2377  }
2378  if ( !dbuf_stat_mask )
2379  {
2380  speedIntrEnable(3);
2381  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2382  if ( (efbits & 1) )
2383  {
2384  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun, ata timedout\n");
2385  return -502;
2386  }
2387  if ( (efbits & 4) )
2388  {
2389  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun, Media Eject\n");
2390  return -550;
2391  }
2392  if ( (dev5_speed_regs->r_spd_intr_stat & 2) )
2393  {
2394  dbuf_stat_mask = dev5_speed_regs->r_spd_dbuf_stat & 0x1F;
2395  }
2396  else
2397  {
2398  if ( (dev5_speed_regs->r_spd_ata_control & 1) )
2399  {
2400  spd_ata_status_tmp = dev5_speed_regs->r_spd_ata_status;
2401  Error = sceAtaGetError();
2402  VERBOSE_KPRINTF(1, "DEV5 ATA: error: cmd err 0x%02x, 0x%02x, while DmaRun\n", spd_ata_status_tmp, Error);
2403  return (!(Error & 0x80)) ? -503 : -510;
2404  }
2405  VERBOSE_KPRINTF(1, "DEV5 ATA: warning: ata intr without error.\n");
2406  continue;
2407  }
2408  }
2409  if ( blksectors < dbuf_stat_mask )
2410  {
2411  dbuf_stat_mask = blksectors;
2412  }
2413  dbuf_stat_sectors = dbuf_stat_mask << 9;
2414  VERBOSE_KPRINTF(
2415  1,
2416  "DmaRun_atapi cnt %d nblk %d secsize %d bcr %08x\n",
2417  dbuf_stat_mask,
2418  blksectors,
2419  blksize,
2420  (dbuf_stat_sectors << 9) | 0x20);
2421  result = SpdDmaTransfer(0, buf, (dbuf_stat_sectors << 9) | 0x20, dir);
2422  buf += dbuf_stat_sectors;
2423  if ( result < 0 )
2424  return result;
2425  }
2426  if ( blkremainder )
2427  {
2428  while ( !(dev5_speed_regs->r_spd_intr_stat & 1) )
2429  ;
2430  dev5_speed_regs->m_spd_unk36 += 512;
2431  VERBOSE_KPRINTF(1, "SpdDmaTransfer buf:%08x bcr:%d dir:%d\n", buf, 0x40020, dir);
2432  if ( dir )
2433  {
2434  memcpy(g_atapi_xfer_buf, buf, blkremainder);
2435  result = SpdDmaTransfer(0, g_atapi_xfer_buf, 0x40020, dir);
2436  if ( result < 0 )
2437  return result;
2438  }
2439  else
2440  {
2441  result = SpdDmaTransfer(0, g_atapi_xfer_buf, 0x40020, 0);
2442  if ( result < 0 )
2443  return result;
2444  memcpy(buf, g_atapi_xfer_buf, blkremainder);
2445  }
2446  }
2447  VERBOSE_KPRINTF(1, "DmaRun_atapi End.\n");
2448  return 0;
2449 }
2450 
2451 static int DmaRun_atapi_extrans1(char *buf, int blkcount, int blksize, int dir)
2452 {
2453  unsigned int blksectors;
2454  int blkremainder;
2455  int i;
2456  unsigned int dbuf_stat_mask;
2457  int result;
2458  u8 Error;
2459  char spd_ata_status_tmp;
2460  unsigned int dbuf_stat_sectors;
2461  u32 efbits;
2462  USE_DEV5_SPEED_REGS();
2463 
2464  VERBOSE_KPRINTF(1, "DmaRun_atapi_extrans start\n");
2465  FpgaLayer2Off();
2466  FpgaClearBuffer();
2467  FpgaXfdir(dir);
2468  blkremainder = (blkcount * blksize) & 0x1FF;
2469  for ( blksectors = (unsigned int)(blkcount * blksize) >> 9; blksectors; blksectors -= dbuf_stat_mask )
2470  {
2471  dbuf_stat_mask = 0;
2472  for ( i = 0; i < 20 && !dbuf_stat_mask; i += 1 )
2473  {
2474  dbuf_stat_mask = dev5_speed_regs->r_spd_dbuf_stat & 0x1F;
2475  }
2476  if ( !dbuf_stat_mask )
2477  {
2478  speedIntrEnable(3);
2479  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2480  if ( (efbits & 1) )
2481  {
2482  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun_atapi_extrans, ata timedout\n");
2483  return -502;
2484  }
2485  if ( (efbits & 4) )
2486  {
2487  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun_atapi_extrans, Media Eject\n");
2488  return -550;
2489  }
2490  if ( (dev5_speed_regs->r_spd_intr_stat & 2) )
2491  {
2492  dbuf_stat_mask = dev5_speed_regs->r_spd_dbuf_stat & 0x1F;
2493  }
2494  else
2495  {
2496  if ( (dev5_speed_regs->r_spd_ata_control & 1) )
2497  {
2498  spd_ata_status_tmp = dev5_speed_regs->r_spd_ata_status;
2499  Error = sceAtaGetError();
2500  VERBOSE_KPRINTF(1, "DEV5 ATA: error: cmd err 0x%02x, 0x%02x, while DmaRun\n", spd_ata_status_tmp, Error);
2501  return (!(Error & 0x80)) ? -503 : -510;
2502  }
2503  VERBOSE_KPRINTF(1, "DEV5 ATA: warning: ata intr without error.\n");
2504  continue;
2505  }
2506  }
2507  if ( blksectors < dbuf_stat_mask )
2508  {
2509  dbuf_stat_mask = blksectors;
2510  }
2511  dbuf_stat_sectors = dbuf_stat_mask << 9;
2512  VERBOSE_KPRINTF(
2513  1,
2514  "DmaRun_atapi_extrans cnt %d nblk %d secsize %d bcr %08x\n",
2515  dbuf_stat_mask,
2516  blksectors,
2517  blksize,
2518  (dbuf_stat_sectors << 9) | 0x20);
2519  result = SpdDmaTransfer_extrans_1(0, buf, (dbuf_stat_sectors << 9) | 0x20, dir);
2520  buf += dbuf_stat_sectors;
2521  if ( result < 0 )
2522  return result;
2523  }
2524  if ( blkremainder )
2525  {
2526  while ( !(dev5_speed_regs->r_spd_intr_stat & 1) )
2527  ;
2528  dev5_speed_regs->m_spd_unk36 += 512;
2529  VERBOSE_KPRINTF(1, "SpdDmaTransfer buf:%08x bcr:%d dir:%d\n", buf, 0x40020, dir);
2530  if ( dir )
2531  {
2532  memcpy(g_atapi_xfer_buf, buf, blkremainder);
2533  result = SpdDmaTransfer_extrans_1(0, g_atapi_xfer_buf, 0x40020, dir);
2534  if ( result < 0 )
2535  return result;
2536  }
2537  else
2538  {
2539  result = SpdDmaTransfer_extrans_1(0, g_atapi_xfer_buf, 0x40020, 0);
2540  if ( result < 0 )
2541  return result;
2542  memcpy(buf, g_atapi_xfer_buf, blkremainder);
2543  }
2544  }
2545  VERBOSE_KPRINTF(1, "DmaRun_atapi_extrans End.\n");
2546  return 0;
2547 }
2548 
2549 static int DmaRun_atapi_extrans2(char *buf, int blkcount, int blksize, int dir)
2550 {
2551  int result;
2552  unsigned int blksectors;
2553  int blkremainder;
2554  int i;
2555  unsigned int fpga_spckcnt;
2556  u8 Error;
2557  int extransres;
2558  iop_sys_clock_t sysclk;
2559  u32 efbits;
2560  USE_DEV5_SPEED_REGS();
2561 
2562  VERBOSE_KPRINTF(1, "DmaRun_atapi_extrans start\n");
2563  FpgaLayer2Off();
2564  FpgaClearBuffer();
2565  FpgaXfdir(dir);
2566  CancelAlarm(AtaAlarmrHandle, 0);
2567  USec2SysClock(0x989680, &sysclk);
2568  result = SetAlarm(&sysclk, AtaAlarmrHandle, 0);
2569  if ( result < 0 )
2570  {
2571  return result;
2572  }
2573  while ( 1 )
2574  {
2575  speedIntrEnable(3);
2576  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2577  if ( (efbits & 1) )
2578  {
2579  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun_atapi_extrans, ata timedout\n");
2580  return -502;
2581  }
2582  if ( (efbits & 4) )
2583  {
2584  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun_atapi_extrans, Media Eject\n");
2585  return -550;
2586  }
2587  if ( (dev5_speed_regs->r_spd_intr_stat & 2) )
2588  {
2589  break;
2590  }
2591  if ( (dev5_speed_regs->r_spd_ata_control & 1) )
2592  {
2593  Error = sceAtaGetError();
2594  VERBOSE_KPRINTF(
2595  1, "DEV5 ATA: error: cmd err 0x%02x, 0x%02x, while DmaRun\n", dev5_speed_regs->r_spd_ata_status, Error);
2596  return (!(Error & 0x80)) ? -503 : -510;
2597  }
2598  VERBOSE_KPRINTF(1, "DEV5 ATA: warning: ata intr without error.\n");
2599  }
2600  dev5_speed_regs->r_spd_dma_ctrl = (dev5_speed_regs->r_spd_rev_1 >= 0x11) ? 6 : 4;
2601  ata_pre_dma_cb();
2602  FpgaLayer1On();
2603  FpgaXfrenOn();
2604  blkremainder = (blkcount * blksize) & 0x1FF;
2605  extransres = 0;
2606  for ( blksectors = (unsigned int)(blkcount * blksize) >> 9; blksectors; blksectors -= fpga_spckcnt )
2607  {
2608  unsigned int fpga_spckcnt_bytes;
2609 
2610  for ( i = 0;; i += 1 )
2611  {
2612  fpga_spckcnt = do_fpga_check_spckcnt();
2613  if ( fpga_spckcnt >= 3 || fpga_spckcnt >= blksectors )
2614  break;
2615  switch ( i / 500 )
2616  {
2617  case 0:
2618  break;
2619  case 1:
2620  DelayThread(100);
2621  break;
2622  default:
2623  DelayThread(10000);
2624  break;
2625  }
2626  PollEventFlag(g_atapi_event_flag, 5, WEF_OR | WEF_CLEAR, &efbits);
2627  if ( (efbits & 1) )
2628  {
2629  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun_atapi_extrans, ata timedout\n");
2630  FpgaXfrenOff();
2631  FpgaLayer1Off();
2632  ata_post_dma_cb();
2633  if ( !(dev5_speed_regs->r_spd_intr_stat & 2) && (dev5_speed_regs->r_spd_ata_control & 1) )
2634  {
2635  Error = sceAtaGetError();
2636  VERBOSE_KPRINTF(
2637  1, "DEV5 ATA: error: cmd err 0x%02x, 0x%02x, while DmaRun\n", dev5_speed_regs->r_spd_ata_status, Error);
2638  return (!(Error & 0x80)) ? -503 : -510;
2639  }
2640  return -502;
2641  }
2642  if ( (efbits & 4) )
2643  {
2644  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun_atapi_extrans, Media Eject\n");
2645  FpgaXfrenOff();
2646  FpgaLayer1Off();
2647  ata_post_dma_cb();
2648  return -550;
2649  }
2650  }
2651  if ( blksectors < fpga_spckcnt )
2652  {
2653  fpga_spckcnt = blksectors;
2654  }
2655  fpga_spckcnt_bytes = fpga_spckcnt << 9;
2656  VERBOSE_KPRINTF(
2657  1,
2658  "DmaRun_atapi_extrans cnt %d nblk %d secsize %d bcr %08x\n",
2659  fpga_spckcnt,
2660  blksectors,
2661  blksize,
2662  (fpga_spckcnt_bytes << 9) | 0x20);
2663  extransres = SpdDmaTransfer_extrans_2(0, buf, (fpga_spckcnt_bytes << 9) | 0x20, dir);
2664  if ( extransres < 0 )
2665  break;
2666  buf += fpga_spckcnt_bytes;
2667  }
2668  FpgaXfrenOff();
2669  FpgaLayer1Off();
2670  ata_post_dma_cb();
2671  if ( extransres >= 0 && blkremainder )
2672  {
2673  while ( !(dev5_speed_regs->r_spd_intr_stat & 1) )
2674  ;
2675  dev5_speed_regs->m_spd_unk36 += 512;
2676  VERBOSE_KPRINTF(1, "SpdDmaTransfer buf:%08x bcr:%d dir:%d\n", buf, 0x40020, dir);
2677  ata_pre_dma_cb();
2678  FpgaLayer1On();
2679  FpgaXfrenOn();
2680  if ( dir )
2681  {
2682  memcpy(g_atapi_xfer_buf, buf, blkremainder);
2683  extransres = SpdDmaTransfer_extrans_2(0, g_atapi_xfer_buf, 0x40020, dir);
2684  }
2685  else
2686  {
2687  extransres = SpdDmaTransfer_extrans_2(0, g_atapi_xfer_buf, 0x40020, 0);
2688  if ( extransres >= 0 )
2689  {
2690  memcpy(buf, g_atapi_xfer_buf, blkremainder);
2691  }
2692  }
2693  FpgaXfrenOff();
2694  FpgaLayer1Off();
2695  ata_post_dma_cb();
2696  }
2697  if ( extransres < 0 )
2698  {
2699  return extransres;
2700  }
2701  VERBOSE_KPRINTF(1, "DmaRun_atapi_extrans End.\n");
2702  return 0;
2703 }
2704 
2705 static void DmaRun_spck(char *buf, unsigned int secsize)
2706 {
2707  unsigned int secsize_sectors;
2708  unsigned int fpga_spckcnt;
2709  USE_DEV5_SPEED_REGS();
2710 
2711  VERBOSE_KPRINTF(1, "DmaRun_spck start\n");
2712  FpgaSpckmodeOn();
2713  FpgaLayer2Off();
2714  FpgaClearBuffer();
2715  FpgaXfdir(0);
2716  for ( secsize_sectors = secsize >> 9; secsize_sectors; secsize_sectors -= fpga_spckcnt )
2717  {
2718  unsigned int fpga_spckcnt_bytes;
2719 
2720  for ( fpga_spckcnt = 0; fpga_spckcnt < 4; fpga_spckcnt = do_fpga_check_spckcnt() )
2721  ;
2722  if ( secsize_sectors < fpga_spckcnt )
2723  {
2724  fpga_spckcnt = secsize_sectors;
2725  }
2726  fpga_spckcnt_bytes = fpga_spckcnt << 9;
2727  VERBOSE_KPRINTF(
2728  1,
2729  "DmaRun_spck cnt %d nblk %d secsize %d bcr %08x\n",
2730  fpga_spckcnt,
2731  secsize_sectors,
2732  secsize,
2733  (fpga_spckcnt_bytes << 9) | 0x20);
2734  if ( SpdDmaTransfer_extrans_3(0, buf, (fpga_spckcnt_bytes << 9) | 0x20, 1) < 0 )
2735  {
2736  FpgaSpckmodeOff();
2737  return;
2738  }
2739  buf += fpga_spckcnt_bytes;
2740  }
2741  if ( (secsize & 0x1FF) )
2742  {
2743  dev5_speed_regs->m_spd_unk36 += 512;
2744  VERBOSE_KPRINTF(1, "SpdDmaTransfer buf:%08x bcr:%d dir:%d\n", buf, 0x40020, 1);
2745  memcpy(g_atapi_xfer_buf, buf, secsize & 0x1FF);
2746  if ( SpdDmaTransfer_extrans_3(0, g_atapi_xfer_buf, 0x40020, 1) < 0 )
2747  {
2748  return;
2749  }
2750  }
2751  FpgaSpckmodeOff();
2752  VERBOSE_KPRINTF(1, "DmaRun_spck End.\n");
2753 }
2754 
2755 static int sceAtaWaitResult(void)
2756 {
2757  int res;
2758  int i;
2759  int intr_stat_msk;
2760  u32 efbits;
2761  int suc;
2762  USE_DEV5_SPEED_REGS();
2763 
2764  suc = 0;
2765  res = 0;
2766  switch ( atad_cmd_state.type )
2767  {
2768  case 1:
2769  case 8:
2770  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2771  if ( (efbits & 1) )
2772  {
2773  res = -502;
2774  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ata timedout while non data command\n");
2775  }
2776  if ( (efbits & 4) )
2777  {
2778  res = -550;
2779  VERBOSE_KPRINTF(1, "DEV5 ATA: error: DmaRun, Media Eject\n");
2780  }
2781  suc = 1;
2782  break;
2783  case 4:
2784  case 5:
2785  case 6:
2786  res = atapi_transfer_wrapper((char *)atad_cmd_state.buf, atad_cmd_state.blkcount, atad_cmd_state.dir);
2787  if ( res )
2788  {
2789  break;
2790  }
2791  intr_stat_msk = 0;
2792  for ( i = 0; i < 100 && !intr_stat_msk; i += 1 )
2793  {
2794  intr_stat_msk = dev5_speed_regs->r_spd_intr_stat & 1;
2795  }
2796  if ( !intr_stat_msk )
2797  {
2798  speedIntrEnable(1);
2799  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2800  if ( (efbits & 1) )
2801  {
2802  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ata timedout, buffer stat %04x\n", dev5_speed_regs->r_spd_dbuf_stat);
2803  VERBOSE_KPRINTF(
2804  1,
2805  "DEV5 ATA: error: istat %x, ienable %x\n",
2806  dev5_speed_regs->r_spd_intr_stat,
2807  dev5_speed_regs->r_spd_intr_mask);
2808  res = -502;
2809  }
2810  if ( (efbits & 4) )
2811  {
2812  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ata eject, buffer stat %04x\n", dev5_speed_regs->r_spd_dbuf_stat);
2813  VERBOSE_KPRINTF(
2814  1,
2815  "DEV5 ATA: error: istat %x, ienable %x\n",
2816  dev5_speed_regs->r_spd_intr_stat,
2817  dev5_speed_regs->r_spd_intr_mask);
2818  res = -550;
2819  }
2820  }
2821  suc = 1;
2822  break;
2823  default:
2824  while ( 1 )
2825  {
2826  res = ata_wait_busy1_busy();
2827  if ( res < 0 )
2828  {
2829  break;
2830  }
2831  atad_cmd_state.blkcount -= 1;
2832  if ( atad_cmd_state.blkcount == 0xFFFFFFFF )
2833  {
2834  suc = 1;
2835  break;
2836  }
2837  res = ata_pio_transfer(&atad_cmd_state);
2838  if ( res < 0 )
2839  {
2840  break;
2841  }
2842  }
2843  break;
2844  }
2845  if ( suc && !res )
2846  {
2847  char status_tmp;
2848 
2849  status_tmp = dev5_speed_regs->r_spd_ata_status;
2850  if ( (status_tmp & 0x80) )
2851  {
2852  res = ata_wait_busy1_busy();
2853  status_tmp = dev5_speed_regs->r_spd_ata_status;
2854  }
2855  if ( (status_tmp & 1) )
2856  {
2857  u8 Error;
2858 
2859  Error = sceAtaGetError();
2860  VERBOSE_KPRINTF(1, "DEV5 ATA: error: cmd err 0x%02x, 0x%02x\n", status_tmp, Error);
2861  res = (Error & 0x80) ? -510 : -503;
2862  }
2863  }
2864  CancelAlarm(AtaAlarmrHandle, 0);
2865  speedLEDCtl(0);
2866  if ( res )
2867  {
2868  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ATA failed, %d\n", res);
2869  }
2870  return res;
2871 }
2872 
2873 int xatapi_6_sceAtaWaitResult(void)
2874 {
2875  int restmp;
2876  iop_event_info_t efinfo;
2877 
2878  if ( vReferEventFlagStatus(g_acmd_evfid, &efinfo) || (efinfo.currBits & 1) )
2879  {
2880  VERBOSE_KPRINTF(1, "sceCdAtapiWaitResult Call Error\n");
2881  return -511;
2882  }
2883  restmp = sceAtaWaitResult();
2884  SetEventFlag(g_acmd_evfid, 1);
2885  return restmp;
2886 }
2887 
2888 static int sceCdAtapiWaitResult_local(void)
2889 {
2890  int res;
2891  int i;
2892  int intr_stat_msk;
2893  u32 efbits;
2894  int padinfo;
2895  USE_DEV5_SPEED_REGS();
2896 
2897  res = 0;
2898  switch ( atad_cmd_state.type_atapi )
2899  {
2900  case 1:
2901  case 8:
2902  VERBOSE_KPRINTF(1, "waitresult\n");
2903  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2904  if ( (efbits & 1) )
2905  {
2906  res = -502;
2907  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ata timedout while non data command\n");
2908  }
2909  if ( (efbits & 4) )
2910  {
2911  res = -550;
2912  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ata eject while non data command\n");
2913  }
2914  break;
2915  case 4:
2916  case 5:
2917  case 6:
2918  VERBOSE_KPRINTF(1, "waitresult dma\n");
2919  if ( !g_reset_scrambling_pack )
2920  {
2921  res = DmaRun_atapi(
2922  (char *)atad_cmd_state.buf_atapi,
2923  atad_cmd_state.blkcount_atapi,
2924  atad_cmd_state.blksize_atapi,
2925  atad_cmd_state.dir_atapi);
2926  }
2927  else if ( atad_cmd_state.dir_atapi )
2928  {
2929  int blktotal1;
2930  int blkoffs;
2931 
2932  blktotal1 = atad_cmd_state.blkcount_atapi * atad_cmd_state.blksize_atapi;
2933  for ( blkoffs = 0; blkoffs < blktotal1;
2934  blkoffs += atad_cmd_state.blkcount_atapi * atad_cmd_state.blksize_atapi )
2935  {
2936  int padres;
2937 
2938  padres = Mpeg2CheckPadding(
2939  (char *)atad_cmd_state.buf_atapi + blkoffs, blktotal1 - blkoffs, &padinfo, &g_pes_scrambling_control_pack);
2940  if ( padres < 0 )
2941  {
2942  res = DmaRun_atapi(
2943  (char *)atad_cmd_state.buf_atapi,
2944  atad_cmd_state.blkcount_atapi,
2945  atad_cmd_state.blksize_atapi,
2946  atad_cmd_state.dir_atapi);
2947  break;
2948  }
2949  atad_cmd_state.blksize_atapi = 2048;
2950  atad_cmd_state.blkcount_atapi = padinfo;
2951  res = padres ?
2952  DmaRun_atapi_extrans1(
2953  (char *)atad_cmd_state.buf_atapi + blkoffs, padinfo, 2048, atad_cmd_state.dir_atapi) :
2954  DmaRun_atapi((char *)atad_cmd_state.buf_atapi + blkoffs, padinfo, 2048, atad_cmd_state.dir_atapi);
2955  }
2956  }
2957  else
2958  {
2959  res = DmaRun_atapi_extrans2(
2960  (char *)atad_cmd_state.buf_atapi, atad_cmd_state.blkcount_atapi, atad_cmd_state.blksize_atapi, 0);
2961  }
2962  if ( res )
2963  {
2964  break;
2965  }
2966  intr_stat_msk = 0;
2967  for ( i = 0; i < 100 && !intr_stat_msk; i += 1 )
2968  {
2969  intr_stat_msk = dev5_speed_regs->r_spd_intr_stat & 1;
2970  }
2971  if ( intr_stat_msk )
2972  {
2973  break;
2974  }
2975  VERBOSE_KPRINTF(1, "ata command not finished yet\n");
2976  speedIntrEnable(1);
2977  WaitEventFlag(g_atapi_event_flag, 7, WEF_OR | WEF_CLEAR, &efbits);
2978  if ( (efbits & 1) )
2979  {
2980  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ata timedout, buffer stat %04x\n", dev5_speed_regs->r_spd_dbuf_stat);
2981  VERBOSE_KPRINTF(
2982  1,
2983  "DEV5 ATA: error: istat %x, ienable %x\n",
2984  dev5_speed_regs->r_spd_intr_stat,
2985  dev5_speed_regs->r_spd_intr_mask);
2986  res = -502;
2987  }
2988  if ( (efbits & 4) )
2989  {
2990  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ata eject, buffer stat %04x\n", dev5_speed_regs->r_spd_dbuf_stat);
2991  VERBOSE_KPRINTF(
2992  1,
2993  "DEV5 ATA: error: istat %x, ienable %x\n",
2994  dev5_speed_regs->r_spd_intr_stat,
2995  dev5_speed_regs->r_spd_intr_mask);
2996  res = -550;
2997  }
2998  break;
2999  default:
3000  res = IoRun_atapi(&atad_cmd_state);
3001  break;
3002  }
3003  if ( !res )
3004  {
3005  char ata_status_tmp;
3006 
3007  ata_status_tmp = dev5_speed_regs->r_spd_ata_status;
3008  if ( (ata_status_tmp & 0x80) )
3009  {
3010  res = ata_wait_busy1_busy();
3011  ata_status_tmp = dev5_speed_regs->r_spd_ata_status;
3012  }
3013  if ( (ata_status_tmp & 1) )
3014  {
3015  u8 Error;
3016 
3017  Error = sceAtaGetError();
3018  VERBOSE_KPRINTF(1, "DEV5 ATA: error: cmd status 0x%02x, error 0x%02x\n", ata_status_tmp, Error);
3019  res = (Error & 0x80) ? -510 : -503;
3020  }
3021  }
3022  CancelAlarm(AtaAlarmrHandle, 0);
3023  speedLEDCtl(0);
3024  VERBOSE_KPRINTF(1, "sceCdAtapiWaitResult_local() End.\n");
3025  if ( res )
3026  {
3027  VERBOSE_KPRINTF(1, "DEV5 ATA: error: ATA failed, %d\n", res);
3028  }
3029  return res;
3030 }
3031 
3032 int xatapi_8_sceCdAtapiWaitResult(void)
3033 {
3034  int restmp;
3035  iop_event_info_t efinfo;
3036 
3037  if ( vReferEventFlagStatus(g_acmd_evfid, &efinfo) || (efinfo.currBits & 1) )
3038  {
3039  VERBOSE_KPRINTF(1, "sceCdAtapiWaitResult Call Error\n");
3040  return -511;
3041  }
3042  restmp = sceCdAtapiWaitResult_local();
3043  SetEventFlag(g_acmd_evfid, 1);
3044  return restmp;
3045 }
3046 
3047 static void ata_bus_reset_inner(void)
3048 {
3049  USE_DEV5_SPEED_REGS();
3050 
3051  dev5_speed_regs->r_spd_if_ctrl = 128;
3052  DelayThread(100);
3053  dev5_speed_regs->r_spd_if_ctrl = 0;
3054  dev5_speed_regs->r_spd_if_ctrl = 72;
3055  DelayThread(3000);
3056  VERBOSE_KPRINTF(1, "hard reset\n");
3057 }
3058 
3059 static int ata_bus_reset(void)
3060 {
3061  USE_DEV5_SPEED_REGS();
3062 
3063  if ( !(dev5_speed_regs->r_spd_if_ctrl & 0x40) )
3064  ata_bus_reset_inner();
3065  return ata_wait_busy2_busy();
3066 }
3067 
3068 int xatapi_4_sceAtaSoftReset(void)
3069 {
3070  USE_DEV5_SPEED_REGS();
3071 
3072  if ( (dev5_speed_regs->r_spd_ata_control & 0x80) )
3073  return -501;
3074  dev5_speed_regs->r_spd_ata_control = 6;
3075  DelayThread(100);
3076  dev5_speed_regs->r_spd_ata_control = 2;
3077  DelayThread(3000);
3078  VERBOSE_KPRINTF(1, "soft reset\n");
3079  return ata_wait_busy1_busy();
3080 }
3081 
3082 #ifdef UNUSED_FUNC
3083 static int sceAtaFlushCache(int device)
3084 {
3085  int result;
3086 
3087  result = xatapi_5_sceAtaExecCmd(0, 1, 0, 0, 0, 0, 0, device << 4, 0xE7, 1);
3088  return result ? result : xatapi_6_sceAtaWaitResult();
3089 }
3090 #endif
3091 
3092 static int ata_device_identify(int device, void *info)
3093 {
3094  int result;
3095 
3096  result = xatapi_5_sceAtaExecCmd(info, 1, 0, 0, 0, 0, 0, device << 4, 0xEC, 2);
3097  return result ? result : xatapi_6_sceAtaWaitResult();
3098 }
3099 
3100 static int ata_device_pkt_identify(int device, void *info)
3101 {
3102  int result;
3103 
3104  result = xatapi_5_sceAtaExecCmd(info, 1, 0, 0, 0, 0, 0, device << 4, 0xA1, 2);
3105  return result ? result : xatapi_6_sceAtaWaitResult();
3106 }
3107 
3108 static int atapi_device_set_transfer_mode(int device, int type, int mode)
3109 {
3110  int result;
3111 
3112  result = xatapi_5_sceAtaExecCmd(0, 1, 3, (u8)(mode | type), 0, 0, 0, device << 4, 0xEF, 1);
3113  if ( result )
3114  return result;
3115  result = xatapi_6_sceAtaWaitResult();
3116  if ( result )
3117  return result;
3118  switch ( type )
3119  {
3120  case 8:
3121  ata_pio_mode(mode);
3122  break;
3123  case 0x20:
3124  ata_multiword_dma_mode(mode);
3125  break;
3126  case 0x40:
3127  ata_ultra_dma_mode(mode);
3128  break;
3129  default:
3130  break;
3131  }
3132  return 0;
3133 }
3134 
3135 static int ata_device_set_transfer_mode(int device, int type, int mode)
3136 {
3137  int result;
3138 
3139  result = sceAtaExecCmd(0, 1, 3, (u8)(mode | type), 0, 0, 0, device << 4, 0xEF, 1);
3140  if ( result )
3141  return result;
3142  result = sceAtaWaitResult();
3143  if ( result )
3144  return result;
3145  switch ( type )
3146  {
3147  case 8:
3148  ata_pio_mode(mode);
3149  break;
3150  case 32:
3151  ata_multiword_dma_mode(mode);
3152  break;
3153  case 64:
3154  ata_ultra_dma_mode(mode);
3155  break;
3156  default:
3157  break;
3158  }
3159  return 0;
3160 }
3161 
3162 static void ata_device_probe(ata_devinfo_t *devinfo)
3163 {
3164  char r_spd_ata_lcyl;
3165  u8 r_spd_ata_hcyl;
3166  USE_DEV5_SPEED_REGS();
3167 
3168  devinfo->exists = 0;
3169  devinfo->has_packet = 2;
3170  if ( (dev5_speed_regs->r_spd_ata_control & 0x88) )
3171  {
3172  VERBOSE_KPRINTF(1, "FindDev ATA_BUSY\n");
3173  return;
3174  }
3175  r_spd_ata_lcyl = dev5_speed_regs->r_spd_ata_lcyl;
3176  r_spd_ata_hcyl = dev5_speed_regs->r_spd_ata_hcyl;
3177  if ( dev5_speed_regs->r_spd_ata_nsector != 1 || dev5_speed_regs->r_spd_ata_sector != 1 )
3178  {
3179  VERBOSE_KPRINTF(1, "FindDev ATA_NOT_CONNECT\n");
3180  return;
3181  }
3182  devinfo->exists = 1;
3183  if ( !r_spd_ata_lcyl && !r_spd_ata_hcyl )
3184  devinfo->has_packet = 0;
3185  if ( r_spd_ata_lcyl == 20 && r_spd_ata_hcyl == 235 )
3186  devinfo->has_packet = 1;
3187  dev5_speed_regs->r_spd_ata_lcyl = 85;
3188  dev5_speed_regs->r_spd_ata_hcyl = 170;
3189  // Unofficial: was 8 bit access
3190  // cppcheck-suppress knownConditionTrueFalse
3191  if ( (dev5_speed_regs->r_spd_ata_lcyl & 0xFF) != 85 || (dev5_speed_regs->r_spd_ata_hcyl & 0xFF) != 170 )
3192  devinfo->exists = 0;
3193 }
3194 
3195 static void atapi_device_set_transfer_mode_outer(int device)
3196 {
3197  if ( g_dma_mode_value )
3198  {
3199  VERBOSE_KPRINTF(0, "UDMA_mode Mode%d\n", 2);
3200  while ( atapi_device_set_transfer_mode(device, 64, (u8)g_dma_speed_value) < 0 )
3201  {
3202  DelayThread(2000000);
3203  }
3204  }
3205  else
3206  {
3207  VERBOSE_KPRINTF(0, "MDMA_mode Mode%d\n", 2);
3208  while ( atapi_device_set_transfer_mode(device, 32, (u8)g_dma_speed_value) < 0 )
3209  {
3210  DelayThread(2000000);
3211  }
3212  }
3213 }
3214 
3215 static void ata_device_set_transfer_mode_outer(int device)
3216 {
3217  int i;
3218 
3219  if ( g_dma_mode_value )
3220  {
3221  VERBOSE_KPRINTF(0, "UDMA_mode Mode%d\n", 2);
3222  for ( i = 0; i < 3 && ata_device_set_transfer_mode(device, 64, (u8)g_dma_speed_value); i += 1 )
3223  {
3224  DelayThread(2000000);
3225  }
3226  }
3227  else
3228  {
3229  VERBOSE_KPRINTF(0, "MDMA_mode Mode%d\n", 2);
3230  for ( i = 0; i < 3 && ata_device_set_transfer_mode(device, 32, (u8)g_dma_speed_value); i += 1 )
3231  {
3232  DelayThread(2000000);
3233  }
3234  }
3235 }
3236 
3237 static void ata_init_devices(ata_devinfo_t *devinfo)
3238 {
3239  int i;
3240  USE_DEV5_SPEED_REGS();
3241 
3242  if ( xatapi_4_sceAtaSoftReset() )
3243  return;
3244  ata_device_probe(&devinfo[0]);
3245  if ( !devinfo[0].exists )
3246  {
3247  VERBOSE_KPRINTF(1, "DEV5 ATA: error: there is no device0\n");
3248  devinfo[1].exists = 0;
3249  return;
3250  }
3251  if ( ata_device_select(1) )
3252  return;
3253  // Unofficial: was 8 bit access
3254  if ( (dev5_speed_regs->r_spd_ata_control & 0xFF) )
3255  ata_device_probe(&devinfo[1]);
3256  else
3257  devinfo[1].exists = 0;
3258  ata_pio_mode(0);
3259  g_is_in_read_info = 0;
3260  for ( i = 0; i < 2; i += 1 )
3261  {
3262  if ( !devinfo[i].exists )
3263  {
3264  continue;
3265  }
3266  if ( !devinfo[i].has_packet )
3267  {
3268  devinfo[i].exists = !ata_device_identify(i, ata_param);
3269  }
3270  if ( devinfo[i].has_packet == 1 )
3271  devinfo[i].exists = !ata_device_pkt_identify(i, ata_param);
3272  VERBOSE_KPRINTF(1, "device%d connected, kind %d.\n", i, devinfo[i].has_packet);
3273  if ( !devinfo[i].exists || devinfo[i].has_packet != 1 )
3274  {
3275  continue;
3276  }
3277  do_hex_dump(ata_param, sizeof(ata_param));
3278  devinfo[i].lba48 = !do_atapi_cmd_inquiry_12h(i);
3279  if ( devinfo[i].lba48 )
3280  {
3281  g_is_in_read_info = 1;
3282  VERBOSE_KPRINTF(0, "Atapi Program Aria Brokun.\n");
3283  continue;
3284  }
3285  atapi_device_set_transfer_mode_outer(i);
3286  }
3287 }
3288 
3289 static void sceAtapiInit(int device)
3290 {
3291  int resetval;
3292  USE_DEV5_SPEED_REGS();
3293 
3294  (void)device;
3295  if ( g_ata_devinfo_init )
3296  return;
3297  g_ata_devinfo_init = 1;
3298  while ( 1 )
3299  {
3300  while ( 1 )
3301  {
3302  resetval = ata_bus_reset();
3303  if ( resetval != -550 )
3304  break;
3305  g_is_wait_busy = 0;
3306  }
3307  if ( !resetval )
3308  break;
3309  dev5_speed_regs->r_spd_if_ctrl = 0;
3310  }
3311  ata_init_devices(atad_devinfo);
3312 }
3313 
3314 static void sceAtInterInit(void)
3315 {
3316  int sc_tmp;
3317 
3318  speedRegisterIntrCb(1, ata_intr_cb);
3319  speedRegisterIntrCb(0, ata_intr_cb);
3320  speedRegisterPreDmaCb(0, ata_pre_dma_cb);
3321  speedRegisterPostDmaCb(0, ata_post_dma_cb);
3322  if ( sceCdSC(0xFFFFFFDC, &sc_tmp) )
3323  speedIntrEnable(256);
3324 }
3325 
3326 static int create_event_flags(void)
3327 {
3328  iop_event_t efparam;
3329 
3330  efparam.attr = EA_SINGLE;
3331  efparam.bits = 0;
3332  g_atapi_event_flag = CreateEventFlag(&efparam);
3333  if ( g_atapi_event_flag < 0 )
3334  return 1;
3335  efparam.attr = EA_MULTI;
3336  efparam.option = 0;
3337  efparam.bits = 1;
3338  g_acmd_evfid = CreateEventFlag(&efparam);
3339  if ( g_acmd_evfid >= 0 )
3340  {
3341  efparam.bits = 1;
3342  g_adma_evfid = CreateEventFlag(&efparam);
3343  if ( g_adma_evfid >= 0 )
3344  {
3345  efparam.bits = 1;
3346  g_io_event_flag = CreateEventFlag(&efparam);
3347  if ( g_io_event_flag >= 0 )
3348  {
3349  sceCdSC(0xFFFFFFE0, &g_acmd_evfid);
3350  sceCdSC(0xFFFFFFDF, &g_adma_evfid);
3351  return 1;
3352  }
3353  }
3354  }
3355  if ( g_atapi_event_flag >= 0 )
3356  DeleteEventFlag(g_atapi_event_flag);
3357  if ( g_acmd_evfid >= 0 )
3358  DeleteEventFlag(g_acmd_evfid);
3359  if ( g_adma_evfid >= 0 )
3360  DeleteEventFlag(g_adma_evfid);
3361  return 0;
3362 }
3363 
3364 static void FpgaLayer1On(void)
3365 {
3366  USE_DEV5_FPGA_REGS();
3367  VERBOSE_KPRINTF(1, "%s():old:FPGA_LAYER1 %x\n", "FpgaLayer1On", dev5_fpga_regs->r_fpga_layer1);
3368  dev5_fpga_regs->r_fpga_layer1 &= ~1;
3369  dev5_fpga_regs->r_fpga_layer1 |= 1;
3370  VERBOSE_KPRINTF(1, "%s():new:FPGA_LAYER1 %x\n", "FpgaLayer1On", dev5_fpga_regs->r_fpga_layer1);
3371 }
3372 
3373 static void FpgaLayer1Off(void)
3374 {
3375  USE_DEV5_FPGA_REGS();
3376 
3377  VERBOSE_KPRINTF(1, "%s():old:FPGA_LAYER1 %x\n", "FpgaLayer1Off", dev5_fpga_regs->r_fpga_layer1);
3378  dev5_fpga_regs->r_fpga_layer1 &= ~1;
3379  VERBOSE_KPRINTF(1, "%s():new:FPGA_LAYER1 %x\n", "FpgaLayer1Off", dev5_fpga_regs->r_fpga_layer1);
3380 }
3381 
3382 #ifdef UNUSED_FUNC
3383 static void FpgaLayer2On(void)
3384 {
3385  USE_DEV5_FPGA_REGS();
3386 
3387  VERBOSE_KPRINTF(1, "%s():old:FPGA_LAYER2 %x\n", "FpgaLayer2On", dev5_fpga_regs->r_fpga_layer2);
3388  dev5_fpga_regs->r_fpga_layer2 &= ~1;
3389  dev5_fpga_regs->r_fpga_layer2 |= 1;
3390  VERBOSE_KPRINTF(1, "%s():new:FPGA_LAYER2 %x\n", "FpgaLayer2On", dev5_fpga_regs->r_fpga_layer2);
3391 }
3392 #endif
3393 
3394 static void FpgaLayer2Off(void)
3395 {
3396  USE_DEV5_FPGA_REGS();
3397 
3398  VERBOSE_KPRINTF(1, "%s():old:FPGA_LAYER2 %x\n", "FpgaLayer2Off", dev5_fpga_regs->r_fpga_layer2);
3399  dev5_fpga_regs->r_fpga_layer2 &= ~1;
3400  VERBOSE_KPRINTF(1, "%s():new:FPGA_LAYER2 %x\n", "FpgaLayer2Off", dev5_fpga_regs->r_fpga_layer2);
3401 }
3402 
3403 static void FpgaXfrenOn(void)
3404 {
3405  USE_DEV5_FPGA_REGS();
3406 
3407  VERBOSE_KPRINTF(1, "%s():old:FPGA_XFREN %x\n", "FpgaXfrenOn", dev5_fpga_regs->r_fpga_xfren);
3408  dev5_fpga_regs->r_fpga_xfren &= ~1;
3409  dev5_fpga_regs->r_fpga_xfren |= 1;
3410  VERBOSE_KPRINTF(1, "%s():new:FPGA_XFREN %x\n", "FpgaXfrenOn", dev5_fpga_regs->r_fpga_xfren);
3411 }
3412 
3413 static void FpgaXfrenOff(void)
3414 {
3415  USE_DEV5_FPGA_REGS();
3416 
3417  VERBOSE_KPRINTF(1, "%s():old:FPGA_XFREN %x\n", "FpgaXfrenOff", dev5_fpga_regs->r_fpga_xfren);
3418  dev5_fpga_regs->r_fpga_xfren &= ~1;
3419  VERBOSE_KPRINTF(1, "%s():new:FPGA_XFREN %x\n", "FpgaXfrenOff", dev5_fpga_regs->r_fpga_xfren);
3420 }
3421 
3422 static void FpgaSpckmodeOn(void)
3423 {
3424  USE_DEV5_FPGA_REGS();
3425 
3426  VERBOSE_KPRINTF(1, "%s():old:FPGA_SPCKMODE %x\n", "FpgaSpckmodeOn", dev5_fpga_regs->r_fpga_spckmode);
3427  dev5_fpga_regs->r_fpga_spckmode &= ~1;
3428  dev5_fpga_regs->r_fpga_spckmode |= 1;
3429  VERBOSE_KPRINTF(1, "%s():new:FPGA_SPCKMODE %x\n", "FpgaSpckmodeOn", dev5_fpga_regs->r_fpga_spckmode);
3430 }
3431 
3432 static void FpgaSpckmodeOff(void)
3433 {
3434  USE_DEV5_FPGA_REGS();
3435 
3436  VERBOSE_KPRINTF(1, "%s():old:FPGA_SPCKMODE %x\n", "FpgaSpckmodeOff", dev5_fpga_regs->r_fpga_spckmode);
3437  dev5_fpga_regs->r_fpga_spckmode &= ~1;
3438  VERBOSE_KPRINTF(1, "%s():new:FPGA_SPCKMODE %x\n", "FpgaSpckmodeOff", dev5_fpga_regs->r_fpga_spckmode);
3439 }
3440 
3441 static void FpgaXfdir(int dir)
3442 {
3443  USE_DEV5_FPGA_REGS();
3444 
3445  VERBOSE_KPRINTF(1, "%s():old:FPGA_XFRDIR %x\n", "FpgaXfrdir", dev5_fpga_regs->r_fpga_xfrdir);
3446  dev5_fpga_regs->r_fpga_xfrdir &= ~1;
3447  if ( dir )
3448  {
3449  dev5_fpga_regs->r_fpga_xfrdir |= 1;
3450  }
3451  VERBOSE_KPRINTF(1, "%s():new:FPGA_XFRDIR %x\n", "FpgaXfrdir", dev5_fpga_regs->r_fpga_xfrdir);
3452 }
3453 
3454 static int FpgaGetRevision(void)
3455 {
3456  USE_DEV5_FPGA_REGS();
3457 
3458  VERBOSE_KPRINTF(1, "%s():FPGA_REVISION %x\n", "FpgaGetRevision", dev5_fpga_regs->r_fpga_revision);
3459  return (u16)dev5_fpga_regs->r_fpga_revision;
3460 }
3461 
3462 #ifdef UNUSED_FUNC
3463 static unsigned int do_fpga_add_unused8120(void)
3464 {
3465  USE_DEV5_FPGA_REGS();
3466 
3467  return (dev5_fpga_regs->r_fpga_sl3bufd + (unsigned int)dev5_fpga_regs->r_fpga_exbufd) >> 7;
3468 }
3469 #endif
3470 
3471 static int do_fpga_check_spckcnt(void)
3472 {
3473  USE_DEV5_FPGA_REGS();
3474 
3475  return (u16)dev5_fpga_regs->r_fpga_spckcnt;
3476 }
3477 
3478 static void FpgaCheckWriteBuffer(void)
3479 {
3480  int i;
3481  USE_DEV5_FPGA_REGS();
3482 
3483  VERBOSE_KPRINTF(1, "%s():in ...\n", "FpgaCheckWriteBuffer");
3484  for ( i = 0; i < 10000 && (dev5_fpga_regs->r_fpga_exbufe || dev5_fpga_regs->r_fpga_sl3bufe); i += 1 )
3485  ;
3486  if ( i == 10000 )
3487  {
3488  VERBOSE_KPRINTF(0, "exbuf enc=%x, sl3buf enc=%x\n", dev5_fpga_regs->r_fpga_exbufe, dev5_fpga_regs->r_fpga_sl3bufe);
3489  }
3490  VERBOSE_KPRINTF(1, "%s():out ...\n", "FpgaCheckWriteBuffer");
3491 }
3492 
3493 static void FpgaCheckWriteBuffer2(void)
3494 {
3495  USE_DEV5_FPGA_REGS();
3496 
3497  VERBOSE_KPRINTF(1, "%s():in ...\n", "FpgaCheckWriteBuffer2");
3498  while ( dev5_fpga_regs->r_fpga_sl3bufd )
3499  {
3500  VERBOSE_KPRINTF(1, "%s():FPGA_SL3BUFD %x\n", "FpgaCheckWriteBuffer2", dev5_fpga_regs->r_fpga_sl3bufd);
3501  VERBOSE_KPRINTF(1, "%s():FPGA_SL3BUFE %x\n", "FpgaCheckWriteBuffer2", dev5_fpga_regs->r_fpga_sl3bufe);
3502  VERBOSE_KPRINTF(1, "%s():FPGA_EXBUFD %x\n", "FpgaCheckWriteBuffer2", dev5_fpga_regs->r_fpga_exbufd);
3503  VERBOSE_KPRINTF(1, "%s():FPGA_EXBUFE %x\n", "FpgaCheckWriteBuffer2", dev5_fpga_regs->r_fpga_exbufe);
3504  }
3505  VERBOSE_KPRINTF(1, "%s():out ...\n", "FpgaCheckWriteBuffer2");
3506 }
3507 
3508 static void FpgaClearBuffer(void)
3509 {
3510  USE_DEV5_FPGA_REGS();
3511 
3512  VERBOSE_KPRINTF(1, "%s():old:FPGA_SL3BUFD %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_sl3bufd);
3513  VERBOSE_KPRINTF(1, "%s():old:FPGA_SL3BUFE %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_sl3bufe);
3514  VERBOSE_KPRINTF(1, "%s():old:FPGA_EXBUFD %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_exbufd);
3515  VERBOSE_KPRINTF(1, "%s():old:FPGA_EXBUFE %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_exbufe);
3516  dev5_fpga_regs->r_fpga_unk30 &= ~1;
3517  dev5_fpga_regs->r_fpga_unk30 |= 1;
3518  while ( (u16)(dev5_fpga_regs->r_fpga_exbufd) || dev5_fpga_regs->r_fpga_sl3bufd )
3519  ;
3520  while ( dev5_fpga_regs->r_fpga_exbufe || dev5_fpga_regs->r_fpga_sl3bufe )
3521  ;
3522  dev5_fpga_regs->r_fpga_unk30 &= ~1;
3523  VERBOSE_KPRINTF(1, "%s():new:FPGA_SL3BUFD %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_sl3bufd);
3524  VERBOSE_KPRINTF(1, "%s():new:FPGA_SL3BUFE %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_sl3bufe);
3525  VERBOSE_KPRINTF(1, "%s():new:FPGA_EXBUFD %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_exbufd);
3526  VERBOSE_KPRINTF(1, "%s():new:FPGA_EXBUFE %x\n", "FpgaClearBuffer", dev5_fpga_regs->r_fpga_exbufe);
3527 }
3528 
3529 static int Mpeg2CheckPadding(char *buf, unsigned int bufsize, int *retptr, int *pesscramblingpackptr)
3530 {
3531  int bufchk;
3532  char *bufoffs1;
3533  const char *bufoffs2;
3534  int i;
3535 
3536  bufchk = 0;
3537  VERBOSE_KPRINTF(1, "%s():in\n", "Mpeg2CheckPadding");
3538  if ( (bufsize & 0x7FF) )
3539  {
3540  VERBOSE_KPRINTF(1, "%s():Buffer size not aligne !!\n", "Mpeg2CheckPadding");
3541  return -1;
3542  }
3543  if ( !*buf && !buf[1] && buf[2] == 1 && (u8)buf[3] == 0xBA )
3544  bufchk = 1;
3545  for ( i = 0; (unsigned int)i < (bufsize >> 11); i += 1 )
3546  {
3547  bufoffs1 = &buf[i << 11];
3548  if ( *bufoffs1 || bufoffs1[1] || bufoffs1[2] != 1 || (u8)bufoffs1[3] != 0xBA )
3549  {
3550  if ( bufchk )
3551  break;
3552  }
3553  else
3554  {
3555  if ( !bufchk )
3556  break;
3557  bufoffs2 = bufoffs1 + 14;
3558  if ( !bufoffs1[14] )
3559  {
3560  if ( !bufoffs1[15] && bufoffs1[16] == 1 && (u8)bufoffs1[17] == 0xBB )
3561  bufoffs2 = bufoffs1 + 38;
3562  if ( !*bufoffs2 && !bufoffs2[1] && bufoffs2[2] == 1 && (u8)bufoffs2[3] != 0xBF && (bufoffs2[6] & 0x60) )
3563  {
3564  *pesscramblingpackptr += 1;
3565  }
3566  }
3567  }
3568  }
3569  VERBOSE_KPRINTF(1, "%s():out %d %s Pack\n", "Mpeg2CheckPadding", i, bufchk ? "RDI" : "NULL");
3570  *retptr = i;
3571  return bufchk;
3572 }
3573 
3574 static int Mpeg2CheckScramble(char *buf, unsigned int bufsize)
3575 {
3576  int restmp;
3577  signed int i;
3578  char *bufcur;
3579  const char *bufbuf;
3580  int buf3;
3581 
3582  restmp = 0;
3583  VERBOSE_KPRINTF(1, "%s():in\n", "Mpeg2CheckScramble");
3584  if ( (bufsize & 0x7FF) )
3585  {
3586  VERBOSE_KPRINTF(1, "%s():Buffer size not aligne !!\n", "Mpeg2CheckScramble");
3587  return 0;
3588  }
3589  for ( i = 0; i < (int)(bufsize >> 11); i += 1 )
3590  {
3591  bufcur = buf + (i << 11);
3592  if ( !*bufcur && !bufcur[1] && bufcur[2] == 1 && (u8)bufcur[3] == 0xBA )
3593  {
3594  bufbuf = bufcur + 14;
3595  if ( !bufcur[14] )
3596  {
3597  if ( !bufcur[15] && bufcur[16] == 1 && (u8)bufcur[17] == 0xBB )
3598  bufbuf = bufcur + 38;
3599  if ( !*bufbuf && !bufbuf[1] && bufbuf[2] == 1 )
3600  {
3601  buf3 = (u8)bufbuf[3];
3602  if ( (buf3 == 0xE0 || buf3 == 0xBD || buf3 == 0xC0 || buf3 == 0xD0) && (bufbuf[6] & 0x30) )
3603  {
3604  restmp = 0xFFFFFFFF;
3605  break;
3606  }
3607  }
3608  }
3609  }
3610  }
3611  VERBOSE_KPRINTF(1, "%s():out\n", "Mpeg2CheckScramble");
3612  return restmp;
3613 }
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