PS2SDK
PS2 Homebrew Libraries
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dmacman.c
1/*
2# _____ ___ ____ ___ ____
3# ____| | ____| | | |____|
4# | ___| |____ ___| ____| | \ PS2DEV Open Source Project.
5#-----------------------------------------------------------------------
6# Copyright 2001-2009, ps2dev - http://www.ps2dev.org
7# Licenced under Academic Free License version 2.0
8# Review ps2sdk README & LICENSE files for further details.
9*/
10
11#include "irx_imports.h"
12#include "dmacman.h"
13
14extern struct irx_export_table _exp_dmacman;
15
16#ifdef _IOP
17IRX_ID("dmacman", 1, 1);
18#endif
19// Based on the module from SCE SDK 1.3.4.
20
21static vu32 *dmac_channel_0_madr = (vu32 *)0xBF801080;
22static vu32 *dmac_channel_0_bcr = (vu32 *)0xBF801084;
23static vu32 *dmac_channel_0_chcr = (vu32 *)0xBF801088;
24static vu32 *dmac_channel_1_madr = (vu32 *)0xBF801090;
25static vu32 *dmac_channel_1_bcr = (vu32 *)0xBF801094;
26static vu32 *dmac_channel_1_chcr = (vu32 *)0xBF801098;
27static vu32 *dmac_channel_2_madr = (vu32 *)0xBF8010A0;
28static vu32 *dmac_channel_2_bcr = (vu32 *)0xBF8010A4;
29static vu32 *dmac_channel_2_chcr = (vu32 *)0xBF8010A8;
30static vu32 *dmac_channel_3_madr = (vu32 *)0xBF8010B0;
31static vu32 *dmac_channel_3_bcr = (vu32 *)0xBF8010B4;
32static vu32 *dmac_channel_3_chcr = (vu32 *)0xBF8010B8;
33static vu32 *dmac_channel_4_madr = (vu32 *)0xBF8010C0;
34static vu32 *dmac_channel_4_bcr = (vu32 *)0xBF8010C4;
35static vu32 *dmac_channel_4_chcr = (vu32 *)0xBF8010C8;
36static vu32 *dmac_channel_4_tadr = (vu32 *)0xBF8010CC;
37static vu32 *dmac_channel_5_madr = (vu32 *)0xBF8010D0;
38static vu32 *dmac_channel_5_bcr = (vu32 *)0xBF8010D4;
39static vu32 *dmac_channel_5_chcr = (vu32 *)0xBF8010D8;
40static vu32 *dmac_channel_6_madr = (vu32 *)0xBF8010E0;
41static vu32 *dmac_channel_6_bcr = (vu32 *)0xBF8010E4;
42static vu32 *dmac_channel_6_chcr = (vu32 *)0xBF8010E8;
43static vu32 *dmac_channel_7_madr = (vu32 *)0xBF801500;
44static vu32 *dmac_channel_7_bcr = (vu32 *)0xBF801504;
45static vu32 *dmac_channel_7_chcr = (vu32 *)0xBF801508;
46static vu32 *dmac_channel_8_madr = (vu32 *)0xBF801510;
47static vu32 *dmac_channel_8_bcr = (vu32 *)0xBF801514;
48static vu32 *dmac_channel_8_chcr = (vu32 *)0xBF801518;
49static vu32 *dmac_channel_9_madr = (vu32 *)0xBF801520;
50static vu32 *dmac_channel_9_bcr = (vu32 *)0xBF801524;
51static vu32 *dmac_channel_9_chcr = (vu32 *)0xBF801528;
52static vu32 *dmac_channel_9_tadr = (vu32 *)0xBF80152C;
53static vu32 *dmac_channel_A_madr = (vu32 *)0xBF801530;
54static vu32 *dmac_channel_A_bcr = (vu32 *)0xBF801534;
55static vu32 *dmac_channel_A_chcr = (vu32 *)0xBF801538;
56static vu32 *dmac_channel_B_madr = (vu32 *)0xBF801540;
57static vu32 *dmac_channel_B_bcr = (vu32 *)0xBF801544;
58static vu32 *dmac_channel_B_chcr = (vu32 *)0xBF801548;
59static vu32 *dmac_channel_C_madr = (vu32 *)0xBF801550;
60static vu32 *dmac_channel_C_bcr = (vu32 *)0xBF801554;
61static vu32 *dmac_channel_C_chcr = (vu32 *)0xBF801558;
62static vu32 *dmac_channel_9_4_9_a = (vu32 *)0xBF801560;
63static vu32 *dmac_channel_A_4_9_a = (vu32 *)0xBF801564;
64static vu32 *dmac_channel_4_4_9_a = (vu32 *)0xBF801568;
65static vu32 *dmac_dpcr = (vu32 *)0xBF8010F0;
66static vu32 *dmac_dpcr2 = (vu32 *)0xBF801570;
67static vu32 *dmac_dpcr3 = (vu32 *)0xBF8015F0;
68static vu32 *dmac_dicr = (vu32 *)0xBF8010F4;
69static vu32 *dmac_dicr2 = (vu32 *)0xBF801574;
70static vu32 *dmac_BF80157C = (vu32 *)0xBF80157C;
71static vu32 *dmac_BF801578 = (vu32 *)0xBF801578;
72
73void dmac_ch_set_madr(u32 channel, u32 val)
74{
75 switch (channel) {
76 case IOP_DMAC_MDECin:
77 *dmac_channel_0_madr = val;
78 break;
79 case IOP_DMAC_MDECout:
80 *dmac_channel_1_madr = val;
81 break;
82 case IOP_DMAC_SIF2:
83 *dmac_channel_2_madr = val;
84 break;
85 case IOP_DMAC_CDVD:
86 *dmac_channel_3_madr = val;
87 break;
88 case IOP_DMAC_SPU:
89 *dmac_channel_4_madr = val;
90 break;
91 case IOP_DMAC_PIO:
92 *dmac_channel_5_madr = val;
93 break;
94 case IOP_DMAC_OTC:
95 *dmac_channel_6_madr = val;
96 break;
97 case IOP_DMAC_SPU2:
98 *dmac_channel_7_madr = val;
99 break;
100 case IOP_DMAC_DEV9:
101 *dmac_channel_8_madr = val;
102 break;
103 case IOP_DMAC_SIF0:
104 *dmac_channel_9_madr = val;
105 break;
106 case IOP_DMAC_SIF1:
107 *dmac_channel_A_madr = val;
108 break;
109 case IOP_DMAC_SIO2in:
110 *dmac_channel_B_madr = val;
111 break;
112 case IOP_DMAC_SIO2out:
113 *dmac_channel_C_madr = val;
114 break;
115 default:
116 break;
117 }
118}
119
120u32 dmac_ch_get_madr(u32 channel)
121{
122 switch (channel) {
123 case IOP_DMAC_MDECin:
124 return *dmac_channel_0_madr;
125 case IOP_DMAC_MDECout:
126 return *dmac_channel_1_madr;
127 case IOP_DMAC_SIF2:
128 return *dmac_channel_2_madr;
129 case IOP_DMAC_CDVD:
130 return *dmac_channel_3_madr;
131 case IOP_DMAC_SPU:
132 return *dmac_channel_4_madr;
133 case IOP_DMAC_PIO:
134 return *dmac_channel_5_madr;
135 case IOP_DMAC_OTC:
136 return *dmac_channel_6_madr;
137 case IOP_DMAC_SPU2:
138 return *dmac_channel_7_madr;
139 case IOP_DMAC_DEV9:
140 return *dmac_channel_8_madr;
141 case IOP_DMAC_SIF0:
142 return *dmac_channel_9_madr;
143 case IOP_DMAC_SIF1:
144 return *dmac_channel_A_madr;
145 case IOP_DMAC_SIO2in:
146 return *dmac_channel_B_madr;
147 case IOP_DMAC_SIO2out:
148 return *dmac_channel_C_madr;
149 default:
150 return 0;
151 }
152}
153
154void dmac_ch_set_bcr(u32 channel, u32 val)
155{
156 switch (channel) {
157 case IOP_DMAC_MDECin:
158 *dmac_channel_0_bcr = val;
159 break;
160 case IOP_DMAC_MDECout:
161 *dmac_channel_1_bcr = val;
162 break;
163 case IOP_DMAC_SIF2:
164 *dmac_channel_2_bcr = val;
165 break;
166 case IOP_DMAC_CDVD:
167 *dmac_channel_3_bcr = val;
168 break;
169 case IOP_DMAC_SPU:
170 *dmac_channel_4_bcr = val;
171 break;
172 case IOP_DMAC_PIO:
173 *dmac_channel_5_bcr = val;
174 break;
175 case IOP_DMAC_OTC:
176 *dmac_channel_6_bcr = val;
177 break;
178 case IOP_DMAC_SPU2:
179 *dmac_channel_7_bcr = val;
180 break;
181 case IOP_DMAC_DEV9:
182 *dmac_channel_8_bcr = val;
183 break;
184 case IOP_DMAC_SIF0:
185 *dmac_channel_9_bcr = val;
186 break;
187 case IOP_DMAC_SIF1:
188 *dmac_channel_A_bcr = val;
189 break;
190 case IOP_DMAC_SIO2in:
191 *dmac_channel_B_bcr = val;
192 break;
193 case IOP_DMAC_SIO2out:
194 *dmac_channel_C_bcr = val;
195 break;
196 default:
197 break;
198 }
199}
200
201u32 dmac_ch_get_bcr(u32 channel)
202{
203 switch (channel) {
204 case IOP_DMAC_MDECin:
205 return *dmac_channel_0_bcr;
206 case IOP_DMAC_MDECout:
207 return *dmac_channel_1_bcr;
208 case IOP_DMAC_SIF2:
209 return *dmac_channel_2_bcr;
210 case IOP_DMAC_CDVD:
211 return *dmac_channel_3_bcr;
212 case IOP_DMAC_SPU:
213 return *dmac_channel_4_bcr;
214 case IOP_DMAC_PIO:
215 return *dmac_channel_5_bcr;
216 case IOP_DMAC_OTC:
217 return *dmac_channel_6_bcr;
218 case IOP_DMAC_SPU2:
219 return *dmac_channel_7_bcr;
220 case IOP_DMAC_DEV9:
221 return *dmac_channel_8_bcr;
222 case IOP_DMAC_SIF0:
223 return *dmac_channel_9_bcr;
224 case IOP_DMAC_SIF1:
225 return *dmac_channel_A_bcr;
226 case IOP_DMAC_SIO2in:
227 return *dmac_channel_B_bcr;
228 case IOP_DMAC_SIO2out:
229 return *dmac_channel_C_bcr;
230 default:
231 return 0;
232 }
233}
234
235void dmac_ch_set_chcr(u32 channel, u32 val)
236{
237 switch (channel) {
238 case IOP_DMAC_MDECin:
239 *dmac_channel_0_chcr = val;
240 break;
241 case IOP_DMAC_MDECout:
242 *dmac_channel_1_chcr = val;
243 break;
244 case IOP_DMAC_SIF2:
245 *dmac_channel_2_chcr = val;
246 break;
247 case IOP_DMAC_CDVD:
248 *dmac_channel_3_chcr = val;
249 break;
250 case IOP_DMAC_SPU:
251 *dmac_channel_4_chcr = val;
252 break;
253 case IOP_DMAC_PIO:
254 *dmac_channel_5_chcr = val;
255 break;
256 case IOP_DMAC_OTC:
257 *dmac_channel_6_chcr = val;
258 break;
259 case IOP_DMAC_SPU2:
260 *dmac_channel_7_chcr = val;
261 break;
262 case IOP_DMAC_DEV9:
263 *dmac_channel_8_chcr = val;
264 break;
265 case IOP_DMAC_SIF0:
266 *dmac_channel_9_chcr = val;
267 break;
268 case IOP_DMAC_SIF1:
269 *dmac_channel_A_chcr = val;
270 break;
271 case IOP_DMAC_SIO2in:
272 *dmac_channel_B_chcr = val;
273 break;
274 case IOP_DMAC_SIO2out:
275 *dmac_channel_C_chcr = val;
276 break;
277 default:
278 break;
279 }
280}
281
282u32 dmac_ch_get_chcr(u32 channel)
283{
284 switch (channel) {
285 case IOP_DMAC_MDECin:
286 return *dmac_channel_0_chcr;
287 case IOP_DMAC_MDECout:
288 return *dmac_channel_1_chcr;
289 case IOP_DMAC_SIF2:
290 return *dmac_channel_2_chcr;
291 case IOP_DMAC_CDVD:
292 return *dmac_channel_3_chcr;
293 case IOP_DMAC_SPU:
294 return *dmac_channel_4_chcr;
295 case IOP_DMAC_PIO:
296 return *dmac_channel_5_chcr;
297 case IOP_DMAC_OTC:
298 return *dmac_channel_6_chcr;
299 case IOP_DMAC_SPU2:
300 return *dmac_channel_7_chcr;
301 case IOP_DMAC_DEV9:
302 return *dmac_channel_8_chcr;
303 case IOP_DMAC_SIF0:
304 return *dmac_channel_9_chcr;
305 case IOP_DMAC_SIF1:
306 return *dmac_channel_A_chcr;
307 case IOP_DMAC_SIO2in:
308 return *dmac_channel_B_chcr;
309 case IOP_DMAC_SIO2out:
310 return *dmac_channel_C_chcr;
311 default:
312 return 0;
313 }
314}
315
316void dmac_ch_set_tadr(u32 channel, u32 val)
317{
318 switch (channel) {
319 case IOP_DMAC_SPU:
320 *dmac_channel_4_tadr = val;
321 break;
322 case IOP_DMAC_SIF0:
323 *dmac_channel_9_tadr = val;
324 break;
325 default:
326 break;
327 }
328}
329
330u32 dmac_ch_get_tadr(u32 channel)
331{
332 switch (channel) {
333 case IOP_DMAC_SPU:
334 return *dmac_channel_4_tadr;
335 case IOP_DMAC_SIF0:
336 return *dmac_channel_9_tadr;
337 default:
338 return 0;
339 }
340}
341
342void dmac_set_4_9_a(u32 channel, u32 val)
343{
344 switch (channel) {
345 case IOP_DMAC_SPU:
346 *dmac_channel_4_4_9_a = val;
347 break;
348 case IOP_DMAC_SIF0:
349 *dmac_channel_9_4_9_a = val;
350 break;
351 case IOP_DMAC_SIF1:
352 *dmac_channel_A_4_9_a = val;
353 break;
354 default:
355 break;
356 }
357}
358
359u32 dmac_get_4_9_a(u32 channel)
360{
361 switch (channel) {
362 case IOP_DMAC_SPU:
363 return *dmac_channel_4_4_9_a;
364 case IOP_DMAC_SIF0:
365 return *dmac_channel_9_4_9_a;
366 case IOP_DMAC_SIF1:
367 return *dmac_channel_A_4_9_a;
368 default:
369 return 0;
370 }
371}
372
373void dmac_set_dpcr(u32 val)
374{
375 *dmac_dpcr = val;
376}
377
378u32 dmac_get_dpcr(void)
379{
380 return *dmac_dpcr;
381}
382
383void dmac_set_dpcr2(u32 val)
384{
385 *dmac_dpcr2 = val;
386}
387
388u32 dmac_get_dpcr2(void)
389{
390 return *dmac_dpcr2;
391}
392
393void dmac_set_dpcr3(u32 val)
394{
395 *dmac_dpcr3 = val;
396}
397
398u32 dmac_get_dpcr3(void)
399{
400 return *dmac_dpcr3;
401}
402
403void dmac_set_dicr(u32 val)
404{
405 *dmac_dicr = val;
406}
407
408u32 dmac_get_dicr(void)
409{
410 return *dmac_dicr;
411}
412
413void dmac_set_dicr2(u32 val)
414{
415 *dmac_dicr2 = val;
416}
417
418u32 dmac_get_dicr2(void)
419{
420 return *dmac_dicr2;
421}
422
423void dmac_set_BF80157C(u32 val)
424{
425 *dmac_BF80157C = val;
426}
427
428u32 dmac_get_BF80157C(void)
429{
430 return *dmac_BF80157C;
431}
432
433void dmac_set_BF801578(u32 val)
434{
435 *dmac_BF801578 = val;
436}
437
438u32 dmac_get_BF801578(void)
439{
440 return *dmac_BF801578;
441}
442
443int _start(int argc, char *argv[])
444{
445 int state;
446
447 (void)argc;
448 (void)argv;
449
450 if (RegisterLibraryEntries(&_exp_dmacman) != 0) {
451 return 1;
452 }
453 CpuSuspendIntr(&state);
454 dmac_set_dpcr(0x7777777);
455 dmac_set_dpcr2(0x7777777);
456 dmac_set_dpcr3(0x777);
457 {
458 int i;
459 for (i = 0; i < 0xD; i += 1) {
460 dmac_ch_set_madr(i, 0);
461 dmac_ch_set_bcr(i, 0);
462 dmac_ch_set_chcr(i, 0);
463 }
464 }
465
466 dmac_ch_set_tadr(IOP_DMAC_SPU, 0);
467 dmac_ch_set_tadr(IOP_DMAC_SIF0, 0);
468 dmac_set_4_9_a(IOP_DMAC_SPU, 0);
469 dmac_set_4_9_a(IOP_DMAC_SIF0, 0);
470 dmac_set_4_9_a(IOP_DMAC_SIF1, 0);
471 dmac_set_BF801578(1);
472 CpuResumeIntr(state);
473 return 0;
474}
475
476int dmacman_deinit()
477{
478 int state;
479
480 CpuSuspendIntr(&state);
481 dmac_set_BF801578(0);
482 {
483 int i;
484 for (i = 0; i < 0xD; i += 1) {
485 u32 value;
486
487 value = dmac_ch_get_chcr(i);
488 if ((value & 0x1000000) != 0) {
489 Kprintf("WARNING:DMA %dch has been continued until shutdown\n", i);
490 }
491 dmac_ch_set_chcr(i, value & (~0x1000000));
492 }
493 }
494
495 CpuResumeIntr(state);
496 return 1;
497}
498
499int sceSetSliceDMA(u32 channel, void *addr, u32 size, u32 count, int dir)
500{
501 if (channel >= 0xD || channel == IOP_DMAC_OTC) {
502 return 0;
503 }
504 dmac_ch_set_madr(channel, (unsigned int)addr & 0xFFFFFF);
505 dmac_ch_set_bcr(channel, (size & 0xFFFF) | (count << 16));
506 dmac_ch_set_chcr(channel, (dir & 1) | 0x200 | ((dir == 0) ? 0x40000000 : 0));
507 return 1;
508}
509
510int dmac_set_dma_chained_spu_sif0(u32 channel, u32 size, u32 tadr)
511{
512 if (channel == IOP_DMAC_SPU || channel == IOP_DMAC_SIF0) {
513 dmac_ch_set_bcr(channel, size & 0xFFFF);
514 dmac_ch_set_chcr(channel, 0x601);
515 dmac_ch_set_tadr(channel, tadr & 0xFFFFFF);
516 return 1;
517 }
518 return 0;
519}
520
521int dmac_set_dma_sif0(u32 channel, u32 size, u32 tadr)
522{
523 if (channel != IOP_DMAC_SIF0) {
524 return 0;
525 }
526 dmac_ch_set_bcr(IOP_DMAC_SIF0, size & 0xFFFF);
527 dmac_ch_set_chcr(IOP_DMAC_SIF0, 0x701);
528 dmac_ch_set_tadr(IOP_DMAC_SIF0, tadr & 0xFFFFFF);
529 return 1;
530}
531
532int dmac_set_dma_sif1(u32 ch, u32 size)
533{
534 if (ch != IOP_DMAC_SIF1) {
535 return 0;
536 }
537 dmac_ch_set_bcr(IOP_DMAC_SIF1, size & 0xFFFF);
538 dmac_ch_set_chcr(IOP_DMAC_SIF1, 0x40000300);
539 return 1;
540}
541
542void sceStartDMA(u32 channel)
543{
544 if (channel < 0xF) {
545 dmac_ch_set_chcr(channel, dmac_ch_get_chcr(channel) | 0x1000000);
546 }
547}
548
549void sceSetDMAPriority(u32 channel, u32 val)
550{
551 int state;
552
553 CpuSuspendIntr(&state);
554 switch (channel) {
555 case IOP_DMAC_MDECin:
556 dmac_set_dpcr((dmac_get_dpcr() & (~0x7)) | (val & 7));
557 break;
558 case IOP_DMAC_MDECout:
559 dmac_set_dpcr((dmac_get_dpcr() & (~0x70)) | ((val & 7) << 4));
560 break;
561 case IOP_DMAC_SIF2:
562 dmac_set_dpcr((dmac_get_dpcr() & (~0x700)) | ((val & 7) << 8));
563 break;
564 case IOP_DMAC_CDVD:
565 dmac_set_dpcr((dmac_get_dpcr() & (~0x7000)) | ((val & 7) << 12));
566 break;
567 case IOP_DMAC_SPU:
568 dmac_set_dpcr((dmac_get_dpcr() & (~0x70000)) | ((val & 7) << 16));
569 break;
570 case IOP_DMAC_PIO:
571 dmac_set_dpcr((dmac_get_dpcr() & (~0x700000)) | ((val & 7) << 20));
572 break;
573 case IOP_DMAC_OTC:
574 dmac_set_dpcr((dmac_get_dpcr() & (~0x7000000)) | ((val & 7) << 24));
575 break;
576 case IOP_DMAC_SPU2:
577 dmac_set_dpcr2((dmac_get_dpcr2() & (~0x7)) | (val & 7));
578 break;
579 case IOP_DMAC_DEV9:
580 dmac_set_dpcr2((dmac_get_dpcr2() & (~0x70)) | ((val & 7) << 4));
581 break;
582 case IOP_DMAC_SIF0:
583 dmac_set_dpcr2((dmac_get_dpcr2() & (~0x700)) | ((val & 7) << 8));
584 break;
585 case IOP_DMAC_SIF1:
586 dmac_set_dpcr2((dmac_get_dpcr2() & (~0x7000)) | ((val & 7) << 12));
587 break;
588 case IOP_DMAC_SIO2in:
589 dmac_set_dpcr2((dmac_get_dpcr2() & (~0x70000)) | ((val & 7) << 16));
590 break;
591 case IOP_DMAC_SIO2out:
592 dmac_set_dpcr2((dmac_get_dpcr2() & (~0x700000)) | ((val & 7) << 20));
593 break;
594 case IOP_DMAC_FDMA0:
595 dmac_set_dpcr3((dmac_get_dpcr3() & (~0x7)) | (val & 7));
596 break;
597 case IOP_DMAC_FDMA1:
598 dmac_set_dpcr3((dmac_get_dpcr3() & (~0x70)) | ((val & 7) << 4));
599 break;
600 case IOP_DMAC_FDMA2:
601 dmac_set_dpcr3((dmac_get_dpcr3() & (~0x700)) | ((val & 7) << 8));
602 break;
603 case IOP_DMAC_CPU:
604 dmac_set_dpcr((dmac_get_dpcr() & (~0x70000000)) | ((val & 7) << 28));
605 break;
606 case IOP_DMAC_USB:
607 dmac_set_dpcr2((dmac_get_dpcr2() & (~0x7000000)) | ((val & 7) << 24));
608 break;
609 default:
610 break;
611 }
612 CpuResumeIntr(state);
613}
614
615void sceEnableDMAChannel(u32 channel)
616{
617 int state;
618
619 CpuSuspendIntr(&state);
620 switch (channel) {
621 case IOP_DMAC_MDECin:
622 dmac_set_dpcr(dmac_get_dpcr() | 0x8);
623 break;
624 case IOP_DMAC_MDECout:
625 dmac_set_dpcr(dmac_get_dpcr() | 0x80);
626 break;
627 case IOP_DMAC_SIF2:
628 dmac_set_dpcr(dmac_get_dpcr() | 0x800);
629 break;
630 case IOP_DMAC_CDVD:
631 dmac_set_dpcr(dmac_get_dpcr() | 0x8000);
632 break;
633 case IOP_DMAC_SPU:
634 dmac_set_dpcr(dmac_get_dpcr() | 0x80000);
635 break;
636 case IOP_DMAC_PIO:
637 dmac_set_dpcr(dmac_get_dpcr() | 0x800000);
638 break;
639 case IOP_DMAC_OTC:
640 dmac_set_dpcr(dmac_get_dpcr() | 0x8000000);
641 break;
642 case IOP_DMAC_SPU2:
643 dmac_set_dpcr2(dmac_get_dpcr2() | 0x8);
644 break;
645 case IOP_DMAC_DEV9:
646 dmac_set_dpcr2(dmac_get_dpcr2() | 0x80);
647 break;
648 case IOP_DMAC_SIF0:
649 dmac_set_dpcr2(dmac_get_dpcr2() | 0x800);
650 break;
651 case IOP_DMAC_SIF1:
652 dmac_set_dpcr2(dmac_get_dpcr2() | 0x8000);
653 break;
654 case IOP_DMAC_SIO2in:
655 dmac_set_dpcr2(dmac_get_dpcr2() | 0x80000);
656 break;
657 case IOP_DMAC_SIO2out:
658 dmac_set_dpcr2(dmac_get_dpcr2() | 0x800000);
659 break;
660 case IOP_DMAC_FDMA0:
661 dmac_set_dpcr3(dmac_get_dpcr3() | 0x8);
662 break;
663 case IOP_DMAC_FDMA1:
664 dmac_set_dpcr3(dmac_get_dpcr3() | 0x80);
665 break;
666 case IOP_DMAC_FDMA2:
667 dmac_set_dpcr3(dmac_get_dpcr3() | 0x800);
668 break;
669 case IOP_DMAC_USB:
670 dmac_set_dpcr2(dmac_get_dpcr2() | 0x8000000);
671 break;
672 default:
673 break;
674 }
675 CpuResumeIntr(state);
676}
677
678void sceDisableDMAChannel(u32 channel)
679{
680 int state;
681
682 CpuSuspendIntr(&state);
683 switch (channel) {
684 case IOP_DMAC_MDECin:
685 dmac_set_dpcr(dmac_get_dpcr() & (~0x8));
686 break;
687 case IOP_DMAC_MDECout:
688 dmac_set_dpcr(dmac_get_dpcr() & (~0x80));
689 break;
690 case IOP_DMAC_SIF2:
691 dmac_set_dpcr(dmac_get_dpcr() & (~0x800));
692 break;
693 case IOP_DMAC_CDVD:
694 dmac_set_dpcr(dmac_get_dpcr() & (~0x8000));
695 break;
696 case IOP_DMAC_SPU:
697 dmac_set_dpcr(dmac_get_dpcr() & (~0x80000));
698 break;
699 case IOP_DMAC_PIO:
700 dmac_set_dpcr(dmac_get_dpcr() & (~0x800000));
701 break;
702 case IOP_DMAC_OTC:
703 dmac_set_dpcr(dmac_get_dpcr() & (~0x8000000));
704 break;
705 case IOP_DMAC_SPU2:
706 dmac_set_dpcr2(dmac_get_dpcr2() & (~0x8));
707 break;
708 case IOP_DMAC_DEV9:
709 dmac_set_dpcr2(dmac_get_dpcr2() & (~0x80));
710 break;
711 case IOP_DMAC_SIF0:
712 dmac_set_dpcr2(dmac_get_dpcr2() & (~0x800));
713 break;
714 case IOP_DMAC_SIF1:
715 dmac_set_dpcr2(dmac_get_dpcr2() & (~0x8000));
716 break;
717 case IOP_DMAC_SIO2in:
718 dmac_set_dpcr2(dmac_get_dpcr2() & (~0x80000));
719 break;
720 case IOP_DMAC_SIO2out:
721 dmac_set_dpcr2(dmac_get_dpcr2() & (~0x800000));
722 break;
723 case IOP_DMAC_FDMA0:
724 dmac_set_dpcr3(dmac_get_dpcr3() & (~0x8));
725 break;
726 case IOP_DMAC_FDMA1:
727 dmac_set_dpcr3(dmac_get_dpcr3() & (~0x80));
728 break;
729 case IOP_DMAC_FDMA2:
730 dmac_set_dpcr3(dmac_get_dpcr3() & (~0x800));
731 break;
732 case IOP_DMAC_USB:
733 dmac_set_dpcr2(dmac_get_dpcr2() & (~0x8000000));
734 break;
735 default:
736 break;
737 }
738 CpuResumeIntr(state);
739}
CpuResumeIntr
int CpuResumeIntr(int state)
Definition intrman.c:227
CpuSuspendIntr
int CpuSuspendIntr(int *state)
Definition intrman.c:205
irx_export_table
Definition irx.h:90
count
u32 count
start sector of fragmented bd/file
Definition usbhdfsd-common.h:1