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#define | DMAC_CHCR_30 (1<<30) |
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#define | DMAC_CHCR_TR (1<<24) |
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#define | DMAC_CHCR_LI (1<<10) |
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#define | DMAC_CHCR_CO (1<<9) |
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#define | DMAC_CHCR_08 (1<<8) |
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#define | DMAC_CHCR_DR (1<<0) |
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#define | DMAC_TO_MEM 0 |
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#define | DMAC_FROM_MEM 1 |
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#define | IOP_DMAC_SIF2_MADR (*(volatile int*)0xBF8010A0) |
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#define | IOP_DMAC_SIF2_BCR (*(volatile int*)0xBF8010A4) |
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#define | IOP_DMAC_SIF2_BCR_size (*(volatile short*)0xBF8010A4) |
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#define | IOP_DMAC_SIF2_BCR_count (*(volatile short*)0xBF8010A6) |
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#define | IOP_DMAC_SIF2_CHCR (*(volatile int*)0xBF8010A8) |
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#define | IOP_DMAC_SIF9_MADR (*(volatile int*)0xBF801520) |
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#define | IOP_DMAC_SIF9_BCR (*(volatile int*)0xBF801524) |
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#define | IOP_DMAC_SIF9_BCR_size (*(volatile short*)0xBF801524) |
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#define | IOP_DMAC_SIF9_BCR_count (*(volatile short*)0xBF801526) |
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#define | IOP_DMAC_SIF9_CHCR (*(volatile int*)0xBF801528) |
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#define | IOP_DMAC_SIF9_TADR (*(volatile int*)0xBF80152C) |
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#define | IOP_DMAC_SIFA_MADR (*(volatile int*)0xBF801530) |
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#define | IOP_DMAC_SIFA_BCR (*(volatile int*)0xBF801534) |
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#define | IOP_DMAC_SIFA_BCR_size (*(volatile short*)0xBF801534) |
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#define | IOP_DMAC_SIFA_BCR_count (*(volatile short*)0xBF801536) |
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#define | IOP_DMAC_SIFA_CHCR (*(volatile int*)0xBF801538) |
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#define | IOP_DMAC_DPCR (*(volatile int*)0xBF8010F0) |
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#define | IOP_DMAC_DPCR2 (*(volatile int*)0xBF801570) |
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#define | dmacman_IMPORTS_start DECLARE_IMPORT_TABLE(dmacman, 1, 1) |
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#define | dmacman_IMPORTS_end END_IMPORT_TABLE |
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#define | I_dmac_ch_set_madr DECLARE_IMPORT(4, dmac_ch_set_madr) |
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#define | I_dmac_ch_get_madr DECLARE_IMPORT(5, dmac_ch_get_madr) |
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#define | I_dmac_ch_set_bcr DECLARE_IMPORT(6, dmac_ch_set_bcr) |
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#define | I_dmac_ch_get_bcr DECLARE_IMPORT(7, dmac_ch_get_bcr) |
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#define | I_dmac_ch_set_chcr DECLARE_IMPORT(8, dmac_ch_set_chcr) |
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#define | I_dmac_ch_get_chcr DECLARE_IMPORT(9, dmac_ch_get_chcr) |
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#define | I_dmac_ch_set_tadr DECLARE_IMPORT(10, dmac_ch_set_tadr) |
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#define | I_dmac_ch_get_tadr DECLARE_IMPORT(11, dmac_ch_get_tadr) |
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#define | I_dmac_set_4_9_a DECLARE_IMPORT(12, dmac_set_4_9_a) |
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#define | I_dmac_get_4_9_a DECLARE_IMPORT(13, dmac_get_4_9_a) |
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#define | I_dmac_set_dpcr DECLARE_IMPORT(14, dmac_set_dpcr) |
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#define | I_dmac_get_dpcr DECLARE_IMPORT(15, dmac_get_dpcr) |
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#define | I_dmac_set_dpcr2 DECLARE_IMPORT(16, dmac_set_dpcr2) |
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#define | I_dmac_get_dpcr2 DECLARE_IMPORT(17, dmac_get_dpcr2) |
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#define | I_dmac_set_dpcr3 DECLARE_IMPORT(18, dmac_set_dpcr3) |
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#define | I_dmac_get_dpcr3 DECLARE_IMPORT(19, dmac_get_dpcr3) |
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#define | I_dmac_set_dicr DECLARE_IMPORT(20, dmac_set_dicr) |
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#define | I_dmac_get_dicr DECLARE_IMPORT(21, dmac_get_dicr) |
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#define | I_dmac_set_dicr2 DECLARE_IMPORT(22, dmac_set_dicr2) |
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#define | I_dmac_get_dicr2 DECLARE_IMPORT(23, dmac_get_dicr2) |
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#define | I_dmac_set_BF80157C DECLARE_IMPORT(24, dmac_set_BF80157C) |
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#define | I_dmac_get_BF80157C DECLARE_IMPORT(25, dmac_get_BF80157C) |
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#define | I_dmac_set_BF801578 DECLARE_IMPORT(26, dmac_set_BF801578) |
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#define | I_dmac_get_BF801578 DECLARE_IMPORT(27, dmac_get_BF801578) |
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#define | I_sceSetSliceDMA DECLARE_IMPORT(28, sceSetSliceDMA) |
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#define | I_dmac_set_dma_chained_spu_sif0 DECLARE_IMPORT(29, dmac_set_dma_chained_spu_sif0) |
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#define | I_dmac_set_dma_sif0 DECLARE_IMPORT(30, dmac_set_dma_sif0) |
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#define | I_dmac_set_dma_sif1 DECLARE_IMPORT(31, dmac_set_dma_sif1) |
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#define | I_sceStartDMA DECLARE_IMPORT(32, sceStartDMA) |
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#define | I_sceSetDMAPriority DECLARE_IMPORT(33, sceSetDMAPriority) |
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#define | I_sceEnableDMAChannel DECLARE_IMPORT(34, sceEnableDMAChannel) |
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#define | I_sceDisableDMAChannel DECLARE_IMPORT(35, sceDisableDMAChannel) |
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#define | dmac_request(...) sceSetSliceDMA(__VA_ARGS__) |
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#define | dmac_transfer(...) sceStartDMA(__VA_ARGS__) |
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#define | dmac_ch_set_dpcr(...) sceSetDMAPriority(__VA_ARGS__) |
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#define | dmac_enable(...) sceEnableDMAChannel(__VA_ARGS__) |
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#define | dmac_disable(...) sceDisableDMAChannel(__VA_ARGS__) |
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#define | I_dmac_request I_sceSetSliceDMA |
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#define | I_dmac_transfer I_sceStartDMA |
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#define | I_dmac_ch_set_dpcr I_sceSetDMAPriority |
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#define | I_dmac_enable I_sceEnableDMAChannel |
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#define | I_dmac_disable I_sceDisableDMAChannel |
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void | dmac_ch_set_madr (u32 channel, u32 val) |
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u32 | dmac_ch_get_madr (u32 channel) |
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void | dmac_ch_set_bcr (u32 channel, u32 val) |
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u32 | dmac_ch_get_bcr (u32 channel) |
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void | dmac_ch_set_chcr (u32 channel, u32 val) |
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u32 | dmac_ch_get_chcr (u32 channel) |
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void | dmac_ch_set_tadr (u32 channel, u32 val) |
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u32 | dmac_ch_get_tadr (u32 channel) |
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void | dmac_set_4_9_a (u32 channel, u32 val) |
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u32 | dmac_get_4_9_a (u32 channel) |
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void | dmac_set_dpcr (u32 val) |
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u32 | dmac_get_dpcr (void) |
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void | dmac_set_dpcr2 (u32 val) |
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u32 | dmac_get_dpcr2 (void) |
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void | dmac_set_dpcr3 (u32 val) |
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u32 | dmac_get_dpcr3 (void) |
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void | dmac_set_dicr (u32 val) |
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u32 | dmac_get_dicr (void) |
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void | dmac_set_dicr2 (u32 val) |
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u32 | dmac_get_dicr2 (void) |
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void | dmac_set_BF80157C (u32 val) |
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u32 | dmac_get_BF80157C (void) |
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void | dmac_set_BF801578 (u32 val) |
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u32 | dmac_get_BF801578 (void) |
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int | sceSetSliceDMA (u32 channel, void *addr, u32 size, u32 count, int dir) |
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int | dmac_set_dma_chained_spu_sif0 (u32 channel, u32 size, u32 tadr) |
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int | dmac_set_dma_sif0 (u32 channel, u32 size, u32 tadr) |
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int | dmac_set_dma_sif1 (u32 ch, u32 size) |
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void | sceStartDMA (u32 channel) |
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void | sceSetDMAPriority (u32 channel, u32 val) |
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void | sceEnableDMAChannel (u32 channel) |
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void | sceDisableDMAChannel (u32 channel) |
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DMACMAN definitions and imports.
Definition in file dmacman.h.