PS2SDK
PS2 Homebrew Libraries
dmacman.h
Go to the documentation of this file.
1 /*
2 # _____ ___ ____ ___ ____
3 # ____| | ____| | | |____|
4 # | ___| |____ ___| ____| | \ PS2DEV Open Source Project.
5 #-----------------------------------------------------------------------
6 # Copyright (c) 2003 Marcus R. Brown <mrbrown@0xd6.org>
7 # Licenced under Academic Free License version 2.0
8 # Review ps2sdk README & LICENSE files for further details.
9 */
10 
16 #ifndef __DMACMAN_H__
17 #define __DMACMAN_H__
18 
19 #include <types.h>
20 #include <irx.h>
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
26 typedef struct _iop_dmac_chan {
27  u32 madr;
28  u32 bcr;
29  u32 chcr;
30 } iop_dmac_chan_t;
31 
32 /* CHCR flags */
33 #define DMAC_CHCR_30 (1<<30)
34 
35 #define DMAC_CHCR_TR (1<<24)
36 
37 #define DMAC_CHCR_LI (1<<10)
38 
39 #define DMAC_CHCR_CO (1<<9)
40 #define DMAC_CHCR_08 (1<<8)
41 
42 #define DMAC_CHCR_DR (1<<0)
43 
44 #define DMAC_TO_MEM 0
45 #define DMAC_FROM_MEM 1
46 
47 //SIF2 DMA ch 2 (GPU)
48 #define IOP_DMAC_SIF2_MADR (*(volatile int*)0xBF8010A0)
49 #define IOP_DMAC_SIF2_BCR (*(volatile int*)0xBF8010A4)
50 #define IOP_DMAC_SIF2_BCR_size (*(volatile short*)0xBF8010A4)
51 #define IOP_DMAC_SIF2_BCR_count (*(volatile short*)0xBF8010A6)
52 #define IOP_DMAC_SIF2_CHCR (*(volatile int*)0xBF8010A8)
53 //SIF0 DMA ch 9
54 #define IOP_DMAC_SIF9_MADR (*(volatile int*)0xBF801520)
55 #define IOP_DMAC_SIF9_BCR (*(volatile int*)0xBF801524)
56 #define IOP_DMAC_SIF9_BCR_size (*(volatile short*)0xBF801524)
57 #define IOP_DMAC_SIF9_BCR_count (*(volatile short*)0xBF801526)
58 #define IOP_DMAC_SIF9_CHCR (*(volatile int*)0xBF801528)
59 #define IOP_DMAC_SIF9_TADR (*(volatile int*)0xBF80152C)
60 //SIF1 DMA ch 10 (0xA)
61 #define IOP_DMAC_SIFA_MADR (*(volatile int*)0xBF801530)
62 #define IOP_DMAC_SIFA_BCR (*(volatile int*)0xBF801534)
63 #define IOP_DMAC_SIFA_BCR_size (*(volatile short*)0xBF801534)
64 #define IOP_DMAC_SIFA_BCR_count (*(volatile short*)0xBF801536)
65 #define IOP_DMAC_SIFA_CHCR (*(volatile int*)0xBF801538)
66 
67 #define IOP_DMAC_DPCR (*(volatile int*)0xBF8010F0)
68 #define IOP_DMAC_DPCR2 (*(volatile int*)0xBF801570)
69 
70 enum _iop_dmac_ch {
71  IOP_DMAC_MDECin, IOP_DMAC_MDECout, IOP_DMAC_SIF2, IOP_DMAC_CDVD,
72  IOP_DMAC_SPU, IOP_DMAC_PIO, IOP_DMAC_OTC, IOP_DMAC_SPU2,
73  IOP_DMAC_DEV9, IOP_DMAC_SIF0, IOP_DMAC_SIF1, IOP_DMAC_SIO2in,
74  IOP_DMAC_SIO2out, IOP_DMAC_FDMA0, IOP_DMAC_FDMA1, IOP_DMAC_FDMA2,
75  IOP_DMAC_CPU = 67, //'C'
76  IOP_DMAC_USB = 85, //'U'
77 };
78 
79 /* Note that these are far from official names. */
80 
81 /* Memory ADdRess */
82 extern void dmac_ch_set_madr(u32 channel, u32 val);
83 extern u32 dmac_ch_get_madr(u32 channel);
84 
85 /* Block Control Register */
86 extern void dmac_ch_set_bcr(u32 channel, u32 val);
87 extern u32 dmac_ch_get_bcr(u32 channel);
88 
89 /* CHannel Control Register */
90 extern void dmac_ch_set_chcr(u32 channel, u32 val);
91 extern u32 dmac_ch_get_chcr(u32 channel);
92 
93 /* Tag ADdRess */
94 extern void dmac_ch_set_tadr(u32 channel, u32 val);
95 extern u32 dmac_ch_get_tadr(u32 channel);
96 
97 extern void dmac_set_4_9_a(u32 channel, u32 val);
98 extern u32 dmac_get_4_9_a(u32 channel);
99 
100 /* Dmac P??? Control Registers */
101 extern void dmac_set_dpcr(u32 val);
102 extern u32 dmac_get_dpcr(void);
103 extern void dmac_set_dpcr2(u32 val);
104 extern u32 dmac_get_dpcr2(void);
105 extern void dmac_set_dpcr3(u32 val);
106 extern u32 dmac_get_dpcr3(void);
107 
108 /* Dmac Interrupt Control Registers */
109 extern void dmac_set_dicr(u32 val);
110 extern u32 dmac_get_dicr(void);
111 extern void dmac_set_dicr2(u32 val);
112 extern u32 dmac_get_dicr2(void);
113 
114 extern void dmac_set_BF80157C(u32 val);
115 extern u32 dmac_get_BF80157C(void);
116 
117 extern void dmac_set_BF801578(u32 val);
118 extern u32 dmac_get_BF801578(void);
119 
120 /* Initialize the given channel and start the transfer. Returns 1 if the
121  transfer was started, and 0 on error. */
122 extern int sceSetSliceDMA(u32 channel, void * addr, u32 size, u32 count, int dir);
123 
124 extern int dmac_set_dma_chained_spu_sif0(u32 channel, u32 size, u32 tadr);
125 extern int dmac_set_dma_sif0(u32 channel, u32 size, u32 tadr);
126 extern int dmac_set_dma_sif1(u32 ch, u32 size);
127 
128 /* Start a transfer on the given channel. */
129 extern void sceStartDMA(u32 channel);
130 
131 /* Set the DPCRn value for a specific channel. */
132 extern void sceSetDMAPriority(u32 channel, u32 val);
133 
134 extern void sceEnableDMAChannel(u32 channel);
135 extern void sceDisableDMAChannel(u32 channel);
136 
137 #define dmacman_IMPORTS_start DECLARE_IMPORT_TABLE(dmacman, 1, 1)
138 #define dmacman_IMPORTS_end END_IMPORT_TABLE
139 
140 #define I_dmac_ch_set_madr DECLARE_IMPORT(4, dmac_ch_set_madr)
141 #define I_dmac_ch_get_madr DECLARE_IMPORT(5, dmac_ch_get_madr)
142 #define I_dmac_ch_set_bcr DECLARE_IMPORT(6, dmac_ch_set_bcr)
143 #define I_dmac_ch_get_bcr DECLARE_IMPORT(7, dmac_ch_get_bcr)
144 #define I_dmac_ch_set_chcr DECLARE_IMPORT(8, dmac_ch_set_chcr)
145 #define I_dmac_ch_get_chcr DECLARE_IMPORT(9, dmac_ch_get_chcr)
146 #define I_dmac_ch_set_tadr DECLARE_IMPORT(10, dmac_ch_set_tadr)
147 #define I_dmac_ch_get_tadr DECLARE_IMPORT(11, dmac_ch_get_tadr)
148 #define I_dmac_set_4_9_a DECLARE_IMPORT(12, dmac_set_4_9_a)
149 #define I_dmac_get_4_9_a DECLARE_IMPORT(13, dmac_get_4_9_a)
150 #define I_dmac_set_dpcr DECLARE_IMPORT(14, dmac_set_dpcr)
151 #define I_dmac_get_dpcr DECLARE_IMPORT(15, dmac_get_dpcr)
152 #define I_dmac_set_dpcr2 DECLARE_IMPORT(16, dmac_set_dpcr2)
153 #define I_dmac_get_dpcr2 DECLARE_IMPORT(17, dmac_get_dpcr2)
154 #define I_dmac_set_dpcr3 DECLARE_IMPORT(18, dmac_set_dpcr3)
155 #define I_dmac_get_dpcr3 DECLARE_IMPORT(19, dmac_get_dpcr3)
156 #define I_dmac_set_dicr DECLARE_IMPORT(20, dmac_set_dicr)
157 #define I_dmac_get_dicr DECLARE_IMPORT(21, dmac_get_dicr)
158 #define I_dmac_set_dicr2 DECLARE_IMPORT(22, dmac_set_dicr2)
159 #define I_dmac_get_dicr2 DECLARE_IMPORT(23, dmac_get_dicr2)
160 #define I_dmac_set_BF80157C DECLARE_IMPORT(24, dmac_set_BF80157C)
161 #define I_dmac_get_BF80157C DECLARE_IMPORT(25, dmac_get_BF80157C)
162 #define I_dmac_set_BF801578 DECLARE_IMPORT(26, dmac_set_BF801578)
163 #define I_dmac_get_BF801578 DECLARE_IMPORT(27, dmac_get_BF801578)
164 #define I_sceSetSliceDMA DECLARE_IMPORT(28, sceSetSliceDMA)
165 #define I_dmac_set_dma_chained_spu_sif0 DECLARE_IMPORT(29, dmac_set_dma_chained_spu_sif0)
166 #define I_dmac_set_dma_sif0 DECLARE_IMPORT(30, dmac_set_dma_sif0)
167 #define I_dmac_set_dma_sif1 DECLARE_IMPORT(31, dmac_set_dma_sif1)
168 #define I_sceStartDMA DECLARE_IMPORT(32, sceStartDMA)
169 #define I_sceSetDMAPriority DECLARE_IMPORT(33, sceSetDMAPriority)
170 #define I_sceEnableDMAChannel DECLARE_IMPORT(34, sceEnableDMAChannel)
171 #define I_sceDisableDMAChannel DECLARE_IMPORT(35, sceDisableDMAChannel)
172 
173 // Backwards-compatibility defines
174 
175 #define dmac_request(...) sceSetSliceDMA(__VA_ARGS__)
176 #define dmac_transfer(...) sceStartDMA(__VA_ARGS__)
177 #define dmac_ch_set_dpcr(...) sceSetDMAPriority(__VA_ARGS__)
178 #define dmac_enable(...) sceEnableDMAChannel(__VA_ARGS__)
179 #define dmac_disable(...) sceDisableDMAChannel(__VA_ARGS__)
180 
181 #define I_dmac_request I_sceSetSliceDMA
182 #define I_dmac_transfer I_sceStartDMA
183 #define I_dmac_ch_set_dpcr I_sceSetDMAPriority
184 #define I_dmac_enable I_sceEnableDMAChannel
185 #define I_dmac_disable I_sceDisableDMAChannel
186 
187 #ifdef __cplusplus
188 }
189 #endif
190 
191 #endif /* __DMACMAN_H__ */
_iop_dmac_chan
Definition: dmacman.h:26
count
u32 count
start sector of fragmented bd/file
Definition: usbhdfsd-common.h:3
irx.h