#include <tamtypes.h>
#include <ee_regs.h>
#include <iop_regs.h>

Include dependency graph for ps2_reg_defs.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	st_PS2_SBUS_Registers

Macros
#define	SIF_XFER_MODE_IN (0 << 0)

#define	SIF_XFER_MODE_OUT (1 << 0)

#define	PS2_IRQ_UNK0 (0)

#define	PS2_IRQ_SBUS (1)

#define	PS2_IRQ_UNK2 (2)

#define	PS2_IRQ_UNK3 (3)

#define	PS2_IRQ_UNK4 (4)

#define	PS2_IRQ_SIF0 (5)

#define	PS2_IRQ_SIF1 (6)

#define	PS2_IRQ_SIF2 (7)

#define	PS2_IRQ_UNK8 (8)

#define	PS2_IRQ_UNK9 (9)

#define	PS2_IRQ_UNK10 (10)

#define	SBUS_CTRL_PGPU_INT (1 << 0)

#define	SBUS_CTRL_MSCLK (1 << 8)

#define	SBUS_CTRL_MSINT (1 << 18)

#define	SBUS_CTRL_PS1_RESET (1 << 19)

#define	R_PS2_SBUS(__base_addr, __reg_no) ((vu32 )((u32)(__base_addr) + (__reg_no 0x10)))

#define	R_EE_SBUS(__reg_no) R_PS2_SBUS(A_EE_SBUS_REG_BASE, (__reg_no))

#define	R_IOP_SBUS(__reg_no) R_PS2_SBUS(A_IOP_SBUS_REG_BASE, (__reg_no))

#define	PS2_SBUS_MS_ADDR (0)

#define	PS2_SBUS_SM_ADDR (1)

#define	PS2_SBUS_MS_FLAG (2)

#define	PS2_SBUS_SM_FLAG (3)

#define	PS2_SBUS_REG4 (4)

#define	PS2_SBUS_REG5 (5)

#define	PS2_SBUS_REG6 (6)

#define	PS2_SBUS_REG7 (7)

#define	PS2_DMA_TO_MEM (0)

#define	PS2_DMA_FROM_MEM (1)

#define	SIF_FLAG_INIT (1 << 16)

Typedefs
typedef struct st_PS2_SBUS_Registers	PS2_SBUS_Registers

Detailed Description

Register definitions

Definition in file ps2_reg_defs.h.

Data Structure Documentation

◆ st_PS2_SBUS_Registers

struct st_PS2_SBUS_Registers

Definition at line 13 of file ps2_reg_defs.h.

Data Fields
vu32	main_addr
vu32	pad0[3]
vu32	sub_addr
vu32	pad1[3]
vu32	ms_flag
vu32	pad2[3]
vu32	sm_flag
vu32	pad3[3]
vu32	reg_40
vu32	pad4[3]
vu32	reg_50
vu32	pad5[3]
vu32	reg_60
vu32	pad6[3]
vu32	reg_70
vu32	pad7[3]

Macro Definition Documentation

◆ SIF_XFER_MODE_IN

#define SIF_XFER_MODE_IN (0 << 0)

Definition at line 35 of file ps2_reg_defs.h.

◆ SIF_XFER_MODE_OUT

#define SIF_XFER_MODE_OUT (1 << 0)

Definition at line 36 of file ps2_reg_defs.h.

◆ PS2_IRQ_UNK0

#define PS2_IRQ_UNK0 (0)

Definition at line 39 of file ps2_reg_defs.h.

◆ PS2_IRQ_SBUS

#define PS2_IRQ_SBUS (1)

Definition at line 40 of file ps2_reg_defs.h.

◆ PS2_IRQ_UNK2

#define PS2_IRQ_UNK2 (2)

Definition at line 41 of file ps2_reg_defs.h.

◆ PS2_IRQ_UNK3

#define PS2_IRQ_UNK3 (3)

Definition at line 42 of file ps2_reg_defs.h.

◆ PS2_IRQ_UNK4

#define PS2_IRQ_UNK4 (4)

Definition at line 43 of file ps2_reg_defs.h.

◆ PS2_IRQ_SIF0

#define PS2_IRQ_SIF0 (5)

Definition at line 44 of file ps2_reg_defs.h.

◆ PS2_IRQ_SIF1

#define PS2_IRQ_SIF1 (6)

Definition at line 45 of file ps2_reg_defs.h.

◆ PS2_IRQ_SIF2

#define PS2_IRQ_SIF2 (7)

Definition at line 46 of file ps2_reg_defs.h.

◆ PS2_IRQ_UNK8

#define PS2_IRQ_UNK8 (8)

Definition at line 47 of file ps2_reg_defs.h.

◆ PS2_IRQ_UNK9

#define PS2_IRQ_UNK9 (9)

Definition at line 48 of file ps2_reg_defs.h.

◆ PS2_IRQ_UNK10

#define PS2_IRQ_UNK10 (10)

Definition at line 49 of file ps2_reg_defs.h.

◆ SBUS_CTRL_PGPU_INT

#define SBUS_CTRL_PGPU_INT (1 << 0)

PS1 GPU interrupt, IOP->EE

Definition at line 52 of file ps2_reg_defs.h.

◆ SBUS_CTRL_MSCLK

#define SBUS_CTRL_MSCLK (1 << 8)

I suspect this is bit 8

Definition at line 55 of file ps2_reg_defs.h.

◆ SBUS_CTRL_MSINT

#define SBUS_CTRL_MSINT (1 << 18)

right? bit 18 is set to interrupt IOP from EE. there should be a corresponding "SMINT" for IOP...

Definition at line 58 of file ps2_reg_defs.h.

◆ SBUS_CTRL_PS1_RESET

#define SBUS_CTRL_PS1_RESET (1 << 19)

PS1 Mode Reset, EE->IOP. Resets IOP into "PS1 Mode" though EE needs to do some initializing first.

Definition at line 61 of file ps2_reg_defs.h.

◆ R_PS2_SBUS

#define R_PS2_SBUS	(	__base_addr,
		__reg_no
	)	((vu32 )((u32)(__base_addr) + (__reg_no 0x10)))

Definition at line 63 of file ps2_reg_defs.h.

◆ R_EE_SBUS

#define R_EE_SBUS ( __reg_no ) R_PS2_SBUS(A_EE_SBUS_REG_BASE, (__reg_no))

Definition at line 65 of file ps2_reg_defs.h.

◆ R_IOP_SBUS

#define R_IOP_SBUS ( __reg_no ) R_PS2_SBUS(A_IOP_SBUS_REG_BASE, (__reg_no))

Definition at line 66 of file ps2_reg_defs.h.

◆ PS2_SBUS_MS_ADDR

#define PS2_SBUS_MS_ADDR (0)

Definition at line 68 of file ps2_reg_defs.h.

◆ PS2_SBUS_SM_ADDR

#define PS2_SBUS_SM_ADDR (1)

Definition at line 69 of file ps2_reg_defs.h.

◆ PS2_SBUS_MS_FLAG

#define PS2_SBUS_MS_FLAG (2)

Definition at line 70 of file ps2_reg_defs.h.

◆ PS2_SBUS_SM_FLAG

#define PS2_SBUS_SM_FLAG (3)

Definition at line 71 of file ps2_reg_defs.h.

◆ PS2_SBUS_REG4

#define PS2_SBUS_REG4 (4)

Definition at line 72 of file ps2_reg_defs.h.

◆ PS2_SBUS_REG5

#define PS2_SBUS_REG5 (5)

Definition at line 73 of file ps2_reg_defs.h.

◆ PS2_SBUS_REG6

#define PS2_SBUS_REG6 (6)

Definition at line 74 of file ps2_reg_defs.h.

◆ PS2_SBUS_REG7

#define PS2_SBUS_REG7 (7)

Definition at line 75 of file ps2_reg_defs.h.

◆ PS2_DMA_TO_MEM

#define PS2_DMA_TO_MEM (0)

Definition at line 78 of file ps2_reg_defs.h.

◆ PS2_DMA_FROM_MEM

#define PS2_DMA_FROM_MEM (1)

Definition at line 79 of file ps2_reg_defs.h.

◆ SIF_FLAG_INIT

#define SIF_FLAG_INIT (1 << 16)

Definition at line 82 of file ps2_reg_defs.h.

Data Structures

Macros

Typedefs