PS2SDK
PS2 Homebrew Libraries
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ps2atad.c
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1/*
2# _____ ___ ____ ___ ____
3# ____| | ____| | | |____|
4# | ___| |____ ___| ____| | \ PS2DEV Open Source Project.
5#-----------------------------------------------------------------------
6# Copyright (c) 2003 Marcus R. Brown <mrbrown@0xd6.org>
7# Licenced under Academic Free License version 2.0
8# Review ps2sdk README & LICENSE files for further details.
9*/
10
22#include <types.h>
23#include <defs.h>
24#include <irx.h>
25#include <loadcore.h>
26#include <thbase.h>
27#include <thevent.h>
28#include <stdio.h>
29#include <sysclib.h>
30#ifdef ATA_USE_DEV9
31#include <dev9.h>
32#endif
33#ifdef ATA_USE_AIFDEV9
34#include <aifdev9.h>
35#endif
36#include <atad.h>
37#ifdef ATA_ENABLE_BDM
38#include <bdm.h>
39#include <errno.h>
40#endif
41
42#ifdef ATA_USE_DEV9
43#include <speedregs.h>
44#endif
45#include <atahw.h>
46
47#define MODNAME "atad"
48// TODO: last sdk 3.1.0 has ATAD module version 2.9 with significant changes.
49// Check what was changed, and maybe port changes.
50// CRC32: C2337807
51IRX_ID(MODNAME, 2, 7);
52
53#define M_PRINTF(format, args...) \
54 printf(MODNAME ": " format, ##args)
55
56#define BANNER "ATA device driver %s - Copyright (c) 2003 Marcus R. Brown\n"
57#define VERSION "v1.2"
58
59#define ATA_XFER_MODE_PIO 0x08
60#ifdef ATA_MWDMA_MODES
61#define ATA_XFER_MODE_MDMA 0x20
62#endif
63#define ATA_XFER_MODE_UDMA 0x40
64
65#define ATA_EV_TIMEOUT 1
66#define ATA_EV_COMPLETE 2
67
68static int ata_devinfo_init = 0;
69static int ata_evflg = -1;
70
71// Workarounds
72static u8 ata_dvrp_workaround = 0; // Please read the comments in _start().
73#ifdef ATA_USE_DEV9
74#ifdef ATA_GAMESTAR_WORKAROUND
75static u8 ata_gamestar_workaround = 0;
76#endif
77#endif
78
79/* Local device info kept for drives 0 and 1. */
80static ata_devinfo_t atad_devinfo[2];
81
82/* Data returned from DEVICE IDENTIFY is kept here. Also, this is used by the
83 security commands to set and unlock the password. */
84static u16 ata_param[256];
85
86/* ATA command info. */
87typedef struct _ata_cmd_info
88{
89 u8 command;
90 u8 type;
91} ata_cmd_info_t;
92
93static const ata_cmd_info_t ata_cmd_table[] = {
94 {ATA_C_NOP, 1},
95 {ATA_C_CFA_REQUEST_EXTENDED_ERROR_CODE, 1},
96 {ATA_C_DEVICE_RESET, 5},
97 {ATA_C_READ_SECTOR, 2},
98 {ATA_C_READ_SECTOR_EXT, 0x82},
99 {ATA_C_READ_DMA_EXT, 0x84},
100 {ATA_C_READ_NATIVE_MAX_ADDRESS_EXT, 0x81},
101 {ATA_C_READ_MULTIPLE_EXT, 0x82},
102 {ATA_C_WRITE_SECTOR, 3},
103 {ATA_C_WRITE_LONG, 8},
104 {ATA_C_WRITE_SECTOR_EXT, 0x83},
105 {ATA_C_WRITE_DMA_EXT, 0x84},
106 {ATA_C_SET_MAX_ADDRESS_EXT, 0x81},
107 {ATA_C_CFA_WRITE_SECTORS_WITHOUT_ERASE, 3},
108 {ATA_C_WRITE_MULTIPLE_EXT, 0x83},
109 {ATA_C_READ_VERIFY_SECTOR, 1},
110 {ATA_C_READ_VERIFY_SECTOR_EXT, 0x81},
111 {ATA_C_SEEK, 1},
112 {ATA_C_CFA_TRANSLATE_SECTOR, 2},
113 {ATA_C_SCE_SECURITY_CONTROL, 7},
114 {ATA_C_EXECUTE_DEVICE_DIAGNOSTIC, 6},
115 {ATA_C_INITIALIZE_DEVICE_PARAMETERS, 1},
116 {ATA_C_DOWNLOAD_MICROCODE, 3},
117 {ATA_C_IDENTIFY_PACKET_DEVICE, 2},
118 {ATA_C_SMART, 7},
119 {ATA_C_CFA_ERASE_SECTORS, 1},
120 {ATA_C_READ_MULTIPLE, 2},
121 {ATA_C_WRITE_MULTIPLE, 3},
122 {ATA_C_SET_MULTIPLE_MODE, 1},
123 {ATA_C_READ_DMA, 4},
124 {ATA_C_WRITE_DMA, 4},
125 {ATA_C_CFA_WRITE_MULTIPLE_WITHOUT_ERASE, 3},
126 {ATA_C_GET_MEDIA_STATUS, 1},
127 {ATA_C_MEDIA_LOCK, 1},
128 {ATA_C_MEDIA_UNLOCK, 1},
129 {ATA_C_STANDBY_IMMEDIATE, 1},
130 {ATA_C_IDLE_IMMEDIATE, 1},
131 {ATA_C_STANDBY, 1},
132 {ATA_C_IDLE, 1},
133 {ATA_C_READ_BUFFER, 2},
134 {ATA_C_CHECK_POWER_MODE, 1},
135 {ATA_C_SLEEP, 1},
136 {ATA_C_FLUSH_CACHE, 1},
137 {ATA_C_WRITE_BUFFER, 3},
138 {ATA_C_FLUSH_CACHE_EXT, 1},
139 {ATA_C_IDENTIFY_DEVICE, 2},
140 {ATA_C_MEDIA_EJECT, 1},
141 {ATA_C_SET_FEATURES, 1},
142 {ATA_C_SECURITY_SET_PASSWORD, 3},
143 {ATA_C_SECURITY_UNLOCK, 3},
144 {ATA_C_SECURITY_ERASE_PREPARE, 1},
145 {ATA_C_SECURITY_ERASE_UNIT, 3},
146 {ATA_C_SECURITY_FREEZE_LOCK, 1},
147 {ATA_C_SECURITY_DISABLE_PASSWORD, 3},
148 {ATA_C_READ_NATIVE_MAX_ADDRESS, 1},
149 {ATA_C_SET_MAX_ADDRESS, 1}};
150#define ATA_CMD_TABLE_SIZE (sizeof ata_cmd_table / sizeof(ata_cmd_info_t))
151
152static const ata_cmd_info_t sec_ctrl_cmd_table[] = {
153 {ATA_SCE_IDENTIFY_DRIVE, 2},
154 {ATA_SCE_SECURITY_ERASE_PREPARE, 1},
155 {ATA_SCE_SECURITY_ERASE_UNIT, 1},
156 {ATA_SCE_SECURITY_FREEZE_LOCK, 1},
157 {ATA_SCE_SECURITY_SET_PASSWORD, 3},
158 {ATA_SCE_SECURITY_UNLOCK, 3},
159 {ATA_SCE_SECURITY_WRITE_ID, 3},
160 {ATA_SCE_SECURITY_READ_ID, 2}};
161#define SEC_CTRL_CMD_TABLE_SIZE (sizeof sec_ctrl_cmd_table / sizeof(ata_cmd_info_t))
162
163static const ata_cmd_info_t smart_cmd_table[] = {
164 {ATA_S_SMART_READ_DATA, 2},
165 {ATA_S_SMART_ENABLE_DISABLE_AUTOSAVE, 1},
166 {ATA_S_SMART_SAVE_ATTRIBUTE_VALUES, 1},
167 {ATA_S_SMART_EXECUTE_OFF_LINE, 1},
168 {ATA_S_SMART_READ_LOG, 2},
169 {ATA_S_SMART_WRITE_LOG, 3},
170 {ATA_S_SMART_ENABLE_OPERATIONS, 1},
171 {ATA_S_SMART_DISABLE_OPERATIONS, 1},
172 {ATA_S_SMART_RETURN_STATUS, 1}};
173#define SMART_CMD_TABLE_SIZE (sizeof smart_cmd_table / sizeof(ata_cmd_info_t))
174
175/* This is the state info tracked between sceAtaExecCmd() and sceAtaWaitResult(). */
176typedef struct _ata_cmd_state
177{
178 s32 type; /* The ata_cmd_info_t type field. */
179 union
180 {
181 void *buf;
182 u8 *buf8;
183 u16 *buf16;
184 };
185 u32 blkcount; /* The number of 512-byte blocks (sectors) to transfer. */
186 s32 dir; /* DMA direction: 0 - to RAM, 1 - from RAM. */
187} ata_cmd_state_t;
188
189static ata_cmd_state_t atad_cmd_state;
190
191#ifdef ATA_ENABLE_BDM
192#define NUM_DEVICES 2
193#define ATA_BD_SECTOR_SIZE 512
194static struct block_device g_ata_bd[NUM_DEVICES];
195#endif
196
197#ifdef ATA_USE_DEV9
198static int ata_intr_cb(int flag);
199#endif
200#ifdef ATA_USE_AIFDEV9
201static int ata_intr_cb(void);
202#endif
203static unsigned int ata_alarm_cb(void *unused);
204
205#ifdef ATA_USE_AIFDEV9
206static void aif_tune_drive(int unit, int mode);
207#endif
208
209#ifdef ATA_USE_DEV9
210static void ata_set_dir(int dir);
211
212static void ata_pio_mode(int mode);
213#ifdef ATA_MWDMA_MODES
214static void ata_multiword_dma_mode(int mode);
215#endif
216static void ata_ultra_dma_mode(int mode);
217#endif
218static void ata_shutdown_cb(void);
219
220int ata_device_sector_io64(int device, void *buf, u64 lba, u32 nsectors, int dir);
221
222#ifdef ATA_ENABLE_BDM
223static int ata_bd_read(struct block_device *bd, u64 sector, void *buffer, u16 count);
224static int ata_bd_write(struct block_device *bd, u64 sector, const void *buffer, u16 count);
225static void ata_bd_flush(struct block_device *bd);
226static int ata_bd_stop(struct block_device *bd);
227#endif
228
229extern struct irx_export_table _exp_atad;
230
231#ifdef ATA_USE_DEV9
232// In v1.04, DMA was enabled in ata_set_dir() instead.
233static void ata_pre_dma_cb(int bcr, int dir)
234{
235 USE_SPD_REGS;
236
237 (void)bcr;
238 (void)dir;
239
240 SPD_REG16(SPD_R_XFR_CTRL) |= 0x80;
241}
242
243static void ata_post_dma_cb(int bcr, int dir)
244{
245 USE_SPD_REGS;
246
247 (void)bcr;
248 (void)dir;
249
250 SPD_REG16(SPD_R_XFR_CTRL) &= ~0x80;
251}
252#endif
253
254static int ata_create_event_flag(void)
255{
256 iop_event_t event;
257
258 event.attr = EA_SINGLE; // In v1.04, EA_MULTI was specified.
259 event.bits = 0;
260 return CreateEventFlag(&event);
261}
262
263int _start(int argc, char *argv[])
264{
265#ifdef ATA_USE_DEV9
266 USE_SPD_REGS;
267#endif
268#ifdef ATA_USE_AIFDEV9
269 USE_AIF_REGS;
270#endif
271 int res;
272
273 (void)argc;
274 (void)argv;
275
276 printf(BANNER, VERSION);
277
278 res = MODULE_NO_RESIDENT_END;
279
280#ifdef ATA_USE_DEV9
281 if (!(SPD_REG16(SPD_R_REV_3) & SPD_CAPS_ATA) || !(SPD_REG16(SPD_R_REV_8) & 0x02)) {
282 M_PRINTF("HDD is not connected, exiting.\n");
283 goto out;
284 }
285
286 /* The PSX (Not the PlayStation or PSOne, but a PS2 with a DVR unit) has got an extra processor (Fujitsu MB91302A, aka the "DVRP") that seems to be emulating the console's PS2 ATA interface.
287 The stock disks of all PSX units are definitely 48-bit LBA compliant because of their capacities, but the DVRP's emulation seems to have a design problem:
288 1. It indicates that 48-bit LBA is supported.
289 2. The 48-bit LBA capacity fields show the true capacity of the disk.
290 3. Accesses to beyond the 28-bit LBA capacity (Which is 40.000GB by default) will result in I/O errors.
291 4. (For some PSX units like the DESR-7500): Double-writes to the ATA registers seem to cause the ATA interface to stall.
292
293 The problem is obviously in the DVRP's firmware, but we currently have no way to fix these bugs because the DVRP is even more heavily secured that the IOP.
294 In the eyes of Sony, there isn't a problem because none of their retail PlayStation 2 software ever supported 48-bit LBA.
295
296 The workaround here is to return the 28-bit LBA as the total size and only use 48-bit LBA commands when required. */
297 ata_dvrp_workaround = (SPD_REG16(SPD_R_REV_3) & SPD_CAPS_DVR) ? 1 : 0;
298#endif
299
300#ifdef ATA_USE_AIFDEV9
301 if (!aifIsDetected()) {
302 M_PRINTF("AIF HDD: controller not found.\n");
303 goto out;
304 }
305 aif_regs[AIF_ATA_TCFG] = 0; // Clear ATA timing configuration.
306#endif
307
308#ifdef ATA_USE_DEV9
309#ifdef ATA_GAMESTAR_WORKAROUND
310 /* Some compatible adaptors may malfunction if transfers are not done according to the old ps2atad design.
311 Official adaptors appear to have a 0x0001 set for this register, but not compatibles.
312 While official I/O to this register are 8-bit, some compatibles have a 0x01 for the lower 8-bits,
313 but the upper 8-bits contain some random value. Hence perform a 16-bit read instead. */
314 if (SPD_REG16(0x20) != 1) {
315 ata_gamestar_workaround = 1;
316 M_PRINTF("Compatible adaptor detected.\n");
317 } else {
318 ata_gamestar_workaround = 0;
319 }
320#endif
321#endif
322
323 if ((ata_evflg = ata_create_event_flag()) < 0) {
324 M_PRINTF("Couldn't create event flag, exiting.\n");
325 goto out;
326 }
327
328#ifdef ATA_USE_DEV9
329 /* In v1.04, PIO mode 0 was set here. In late versions, it is set in ata_init_devices(). */
330 SpdRegisterIntrHandler(1, &ata_intr_cb);
331 SpdRegisterIntrHandler(0, &ata_intr_cb);
332#ifdef ATA_GAMESTAR_WORKAROUND
333 if (!ata_gamestar_workaround) {
334#endif
335 dev9RegisterPreDmaCb(0, &ata_pre_dma_cb);
336 dev9RegisterPostDmaCb(0, &ata_post_dma_cb);
337#ifdef ATA_GAMESTAR_WORKAROUND
338 }
339#endif
340 /* Register this at the last position, as it should be the last thing done before shutdown. */
341 Dev9RegisterPowerOffHandler(15, &ata_shutdown_cb);
342#endif
343
344#ifdef ATA_USE_AIFDEV9
345 aifRegisterIntrCb(AIF_INUM_ATA0, &ata_intr_cb);
346 aifRegisterShutdownCb(AIF_INUM_ATA0, &ata_shutdown_cb);
347
348 M_PRINTF("AIF HDD initialized.\n");
349#endif
350
351#ifdef ATA_ENABLE_BDM
352 {
353 int i;
354
355 for (i = 0; i < NUM_DEVICES; ++i) {
356 g_ata_bd[i].priv = (void *)&atad_devinfo[i];
357 g_ata_bd[i].name = "ata";
358 g_ata_bd[i].devNr = i;
359 g_ata_bd[i].parNr = 0;
360 g_ata_bd[i].parId = 0x00;
361 g_ata_bd[i].sectorSize = 512;
362 g_ata_bd[i].sectorOffset = 0;
363 g_ata_bd[i].sectorCount = 0;
364
365 g_ata_bd[i].read = ata_bd_read;
366 g_ata_bd[i].write = ata_bd_write;
367 g_ata_bd[i].flush = ata_bd_flush;
368 g_ata_bd[i].stop = ata_bd_stop;
369 }
370 }
371
372 sceAtaInit(0);
373 sceAtaInit(1);
374#endif
375
376 if (RegisterLibraryEntries(&_exp_atad) != 0) {
377 M_PRINTF("Library is already registered, exiting.\n");
378 goto out;
379 }
380
381 res = MODULE_RESIDENT_END;
382 M_PRINTF("Driver loaded.\n");
383out:
384 return res;
385}
386
387int _exit(void) { return MODULE_RESIDENT_END; }
388
389#ifdef ATA_USE_DEV9
390static int ata_intr_cb(int flag)
391{
392 if (flag == 1) { /* New card, invalidate device info. */
393 memset(atad_devinfo, 0, sizeof atad_devinfo);
394 } else {
395 SpdIntrDisable(SPD_INTR_ATA);
396 iSetEventFlag(ata_evflg, ATA_EV_COMPLETE);
397 }
398
399 return 1;
400}
401#endif
402
403#ifdef ATA_USE_AIFDEV9
404static int ata_intr_cb(void)
405{
406 aifIntrDisable(AIF_INTR_ATA0);
407 iSetEventFlag(ata_evflg, ATA_EV_COMPLETE);
408
409 return 1;
410}
411#endif
412
413static unsigned int ata_alarm_cb(void *unused)
414{
415 (void)unused;
416
417 iSetEventFlag(ata_evflg, ATA_EV_TIMEOUT);
418 return 0;
419}
420
421/* Export 8 */
422int sceAtaGetError(void)
423{
424#ifdef ATA_USE_DEV9
425 USE_ATA_REGS;
426#endif
427#ifdef ATA_USE_AIFDEV9
428 USE_AIF_ATA_REGS;
429#endif
430 return ata_hwport->r_error & 0xff;
431}
432
433#define ATA_WAIT_BUSY 0x80
434#define ATA_WAIT_BUSBUSY 0x88
435
436#define ata_wait_busy() gen_ata_wait_busy(ATA_WAIT_BUSY)
437#define ata_wait_bus_busy() gen_ata_wait_busy(ATA_WAIT_BUSBUSY)
438
439/* 0x80 for busy, 0x88 for bus busy.
440 In the original ATAD, the busy and bus-busy functions were separate, but similar. */
441static int gen_ata_wait_busy(int bits)
442{
443#ifdef ATA_USE_DEV9
444 USE_ATA_REGS;
445#endif
446#ifdef ATA_USE_AIFDEV9
447 USE_AIF_ATA_REGS;
448#endif
449 int i, delay;
450
451 for (i = 0; i < 80; i++) {
452 int didx;
453
454 if (!(ata_hwport->r_control & bits))
455 return 0;
456
457 didx = i / 10;
458 switch (didx) {
459 case 0:
460 continue;
461 case 1:
462 delay = 100;
463 break;
464 case 2:
465 delay = 1000;
466 break;
467 case 3:
468 delay = 10000;
469 break;
470 case 4:
471 delay = 100000;
472 break;
473 default:
474 delay = 1000000;
475 }
476
477 DelayThread(delay);
478 }
479
480 M_PRINTF("Timeout while waiting on busy (0x%02x).\n", bits);
481 return ATA_RES_ERR_TIMEOUT;
482}
483
484static int ata_device_select(int device)
485{
486#ifdef ATA_USE_DEV9
487 USE_ATA_REGS;
488#endif
489#ifdef ATA_USE_AIFDEV9
490 USE_AIF_ATA_REGS;
491#endif
492 int res;
493
494 if ((res = ata_wait_bus_busy()) < 0)
495 return res;
496
497 /* If the device was already selected, nothing to do. */
498 if (((ata_hwport->r_select >> 4) & 1) == device)
499 return 0;
500
501 /* Select the device. */
502 ata_hwport->r_select = (device & 1) << 4;
503 (void)(ata_hwport->r_control);
504 (void)(ata_hwport->r_control); // Only done once in v1.04.
505
506 return ata_wait_bus_busy();
507}
508
509/* Export 6 */
510/*
511 28-bit LBA:
512 sector (7:0) -> LBA (7:0)
513 lcyl (7:0) -> LBA (15:8)
514 hcyl (7:0) -> LBA (23:16)
515 device (3:0) -> LBA (27:24)
516
517 48-bit LBA just involves writing the upper 24 bits in the format above into each respective register on the first write pass, before writing the lower 24 bits in the 2nd write pass. The LBA bits within the device field are not used in either write pass.
518*/
519int sceAtaExecCmd(void *buf, u32 blkcount, u16 feature, u16 nsector, u16 sector, u16 lcyl, u16 hcyl, u16 select, u16 command)
520{
521#ifdef ATA_USE_DEV9
522 USE_ATA_REGS;
523#endif
524#ifdef ATA_USE_AIFDEV9
525 USE_AIF_ATA_REGS;
526#endif
527 iop_sys_clock_t cmd_timeout;
528 const ata_cmd_info_t *cmd_table;
529 int i, res, type, cmd_table_size;
530 int using_timeout, device = (select >> 4) & 1;
531 u8 searchcmd;
532
533 ClearEventFlag(ata_evflg, 0);
534
535 if (!atad_devinfo[device].exists)
536 return ATA_RES_ERR_NODEV;
537
538 if ((res = ata_device_select(device)) != 0)
539 return res;
540
541 /* For the SCE and SMART commands, we need to search on the subcommand
542 specified in the feature register. */
543 if (command == ATA_C_SCE_SECURITY_CONTROL) {
544 cmd_table = sec_ctrl_cmd_table;
545 cmd_table_size = SEC_CTRL_CMD_TABLE_SIZE;
546 searchcmd = (u8)feature;
547 } else if (command == ATA_C_SMART) {
548 cmd_table = smart_cmd_table;
549 cmd_table_size = SMART_CMD_TABLE_SIZE;
550 searchcmd = (u8)feature;
551 } else {
552 cmd_table = ata_cmd_table;
553 cmd_table_size = ATA_CMD_TABLE_SIZE;
554 searchcmd = (u8)command;
555 }
556
557 type = 0;
558 for (i = 0; i < cmd_table_size; i++) {
559 if (searchcmd == cmd_table[i].command) {
560 type = cmd_table[i].type;
561 break;
562 }
563 }
564
565 if (!(atad_cmd_state.type = type & 0x7F)) // Non-SONY: ignore the 48-bit LBA flag.
566 return ATA_RES_ERR_CMD;
567
568 atad_cmd_state.buf = buf;
569 atad_cmd_state.blkcount = blkcount;
570
571 /* Check that the device is ready if this the appropiate command. */
572 if (!(ata_hwport->r_control & 0x40)) {
573 switch (command) {
574 case ATA_C_DEVICE_RESET:
575 case ATA_C_EXECUTE_DEVICE_DIAGNOSTIC:
576 case ATA_C_INITIALIZE_DEVICE_PARAMETERS:
577 case ATA_C_PACKET:
578 case ATA_C_IDENTIFY_PACKET_DEVICE:
579 break;
580 default:
581 M_PRINTF("Error: Device %d is not ready.\n", device);
582 return ATA_RES_ERR_NOTREADY;
583 }
584 }
585
586 /* Does this command need a timeout? */
587 using_timeout = 0;
588 switch (type & 0x7F) { // Non-SONY: ignore the 48-bit LBA flag.
589 case 1:
590 case 6:
591 using_timeout = 1;
592 break;
593 case 4:
594 atad_cmd_state.dir = (command != ATA_C_READ_DMA && command != ATA_C_READ_DMA_EXT);
595 using_timeout = 1;
596 break;
597 }
598
599 if (using_timeout) {
600 cmd_timeout.lo = 0x41eb0000;
601 cmd_timeout.hi = 0;
602
603 /* SECURITY ERASE UNIT needs a bit more time. */
604 if (command == ATA_C_SCE_SECURITY_CONTROL && feature == ATA_SCE_SECURITY_ERASE_UNIT)
605 USec2SysClock(180000000, &cmd_timeout);
606
607 if ((res = SetAlarm(&cmd_timeout, &ata_alarm_cb, NULL)) < 0)
608 return res;
609 }
610
611 /* Enable the command completion interrupt. */
612 if ((type & 0x7F) == 1) {
613#ifdef ATA_USE_DEV9
614 SpdIntrEnable(SPD_INTR_ATA0);
615#endif
616#ifdef ATA_USE_AIFDEV9
617 aifIntrEnable(AIF_INTR_ATA0);
618#endif
619 }
620
621 /* Finally! We send off the ATA command with arguments. */
622 ata_hwport->r_control = (using_timeout == 0) << 1;
623
624 if (type & 0x80) { // For the sake of achieving improved performance, write the registers twice only if required! This is also required for compatibility with the buggy firmware of certain PSX units.
625 /* 48-bit LBA requires writing to the address registers twice,
626 24 bits of the LBA address is written each time.
627 Writing to registers twice does not affect 28-bit LBA since
628 only the latest data stored in address registers is used. */
629 ata_hwport->r_feature = (feature >> 8) & 0xff;
630 ata_hwport->r_nsector = (nsector >> 8) & 0xff;
631 ata_hwport->r_sector = (sector >> 8) & 0xff;
632 ata_hwport->r_lcyl = (lcyl >> 8) & 0xff;
633 ata_hwport->r_hcyl = (hcyl >> 8) & 0xff;
634 }
635
636 ata_hwport->r_feature = feature & 0xff;
637 ata_hwport->r_nsector = nsector & 0xff;
638 ata_hwport->r_sector = sector & 0xff;
639 ata_hwport->r_lcyl = lcyl & 0xff;
640 ata_hwport->r_hcyl = hcyl & 0xff;
641 ata_hwport->r_select = (select | ATA_SEL_LBA) & 0xff; // In v1.04, LBA was enabled in the sceAtaDmaTransfer function.
642 ata_hwport->r_command = command & 0xff;
643
644#ifdef ATA_USE_DEV9
645 /* Turn on the LED. */
646 SpdSetLED(1);
647#endif
648
649 return 0;
650}
651
652/* Do a PIO transfer, to or from the device. */
653static int ata_pio_transfer(ata_cmd_state_t *cmd_state)
654{
655#ifdef ATA_USE_DEV9
656 USE_ATA_REGS;
657#endif
658#ifdef ATA_USE_AIFDEV9
659 USE_AIF_ATA_REGS;
660#endif
661 u16 *buf16;
662 int i, type;
663 u16 status = ata_hwport->r_status & 0xff;
664
665 if (status & ATA_STAT_ERR) {
666 M_PRINTF("Error: PIO cmd error: status 0x%02x, error 0x%02x.\n", status, sceAtaGetError());
667 return ATA_RES_ERR_IO;
668 }
669
670 /* DRQ must be set (data request). */
671 if (!(status & ATA_STAT_DRQ))
672 return ATA_RES_ERR_NODATA;
673
674 type = cmd_state->type;
675
676 if (type == 3 || type == 8) {
677 /* PIO data out */
678 buf16 = cmd_state->buf16;
679 for (i = 0; i < 256; i++) {
680 ata_hwport->r_data = *buf16;
681 cmd_state->buf16 = ++buf16;
682 }
683 if (cmd_state->type == 8) {
684 u8 *buf8;
685
686 buf8 = cmd_state->buf8;
687 for (i = 0; i < 4; i++) {
688 ata_hwport->r_data = *buf8;
689 cmd_state->buf8 = ++buf8;
690 }
691 }
692 } else if (type == 2) {
693 /* PIO data in */
694 buf16 = cmd_state->buf16;
695 for (i = 0; i < 256; i++) {
696 *buf16 = ata_hwport->r_data;
697 cmd_state->buf16 = ++buf16;
698 }
699 }
700
701 return 0;
702}
703
704#ifdef ATA_USE_DEV9
705/* Complete a DMA transfer, to or from the device. */
706static int ata_dma_complete(void *buf, u32 blkcount, int dir)
707{
708 USE_ATA_REGS;
709 USE_SPD_REGS;
710 u32 bits, count, nbytes;
711 int i, res;
712 u16 dma_stat;
713
714 while (blkcount) {
715 for (i = 0; i < 20; i++)
716 if ((dma_stat = SPD_REG16(0x38) & 0x1f))
717 goto next_transfer;
718
719 if (dma_stat)
720 goto next_transfer;
721
722 SpdIntrEnable(SPD_INTR_ATA);
723 /* Wait for the previous transfer to complete or a timeout. */
724 WaitEventFlag(ata_evflg, ATA_EV_TIMEOUT | ATA_EV_COMPLETE, WEF_CLEAR | WEF_OR, &bits);
725
726 if (bits & ATA_EV_TIMEOUT) { /* Timeout. */
727 M_PRINTF("Error: DMA timeout.\n");
728 return ATA_RES_ERR_TIMEOUT;
729 }
730 /* No DMA completion bit? Spurious interrupt. */
731 if (!(SPD_REG16(SPD_R_INTR_STAT) & 0x02)) {
732 if (ata_hwport->r_control & 0x01) {
733 M_PRINTF("Error: Command error while doing DMA.\n");
734 M_PRINTF("Error: Command error status 0x%02x, error 0x%02x.\n", ata_hwport->r_status, sceAtaGetError());
735 /* In v1.04, there was no check for ICRC. */
736 return ((sceAtaGetError() & ATA_ERR_ICRC) ? ATA_RES_ERR_ICRC : ATA_RES_ERR_IO);
737 } else {
738 M_PRINTF("Warning: Got command interrupt, but not an error.\n");
739 continue;
740 }
741 }
742
743 dma_stat = SPD_REG16(0x38) & 0x1f;
744
745 next_transfer:
746 count = (blkcount < dma_stat) ? blkcount : dma_stat;
747 nbytes = count * 512;
748 if ((res = SpdDmaTransfer(0, buf, (nbytes << 9) | 32, dir)) < 0)
749 return res;
750
751 buf = (void *)((u8 *)buf + nbytes);
752 blkcount -= count;
753 }
754
755 return 0;
756}
757#endif
758
759/* Export 7 */
760int sceAtaWaitResult(void)
761{
762#ifdef ATA_USE_DEV9
763 USE_SPD_REGS;
764 USE_ATA_REGS;
765#endif
766#ifdef ATA_USE_AIFDEV9
767 USE_AIF_ATA_REGS;
768#endif
769 ata_cmd_state_t *cmd_state = &atad_cmd_state;
770 u32 bits;
771 int res = 0, type = cmd_state->type;
772 u16 stat;
773
774 if (type == 1 || type == 6) { /* Non-data commands. */
775 WaitEventFlag(ata_evflg, ATA_EV_TIMEOUT | ATA_EV_COMPLETE, WEF_CLEAR | WEF_OR, &bits);
776 if (bits & ATA_EV_TIMEOUT) { /* Timeout. */
777 M_PRINTF("Error: ATA timeout on a non-data command.\n");
778 return ATA_RES_ERR_TIMEOUT;
779 }
780 } else if (type == 4) { /* DMA. */
781#ifdef ATA_USE_DEV9
782 int i;
783
784 if ((res = ata_dma_complete(cmd_state->buf, cmd_state->blkcount,
785 cmd_state->dir)) < 0)
786 goto finish;
787
788 for (i = 0; i < 100; i++)
789 if ((stat = SPD_REG16(SPD_R_INTR_STAT) & 0x01))
790 break;
791 if (!stat) {
792 SpdIntrEnable(SPD_INTR_ATA0);
793 WaitEventFlag(ata_evflg, ATA_EV_TIMEOUT | ATA_EV_COMPLETE, WEF_CLEAR | WEF_OR, &bits);
794 if (bits & ATA_EV_TIMEOUT) {
795 M_PRINTF("Error: ATA timeout on DMA completion, buffer stat %04x\n", SPD_REG16(0x38));
796 M_PRINTF("Error: istat %x, ienable %x\n", SPD_REG16(SPD_R_INTR_STAT), SPD_REG16(SPD_R_INTR_MASK));
797 res = ATA_RES_ERR_TIMEOUT;
798 }
799 }
800#endif
801#ifdef ATA_USE_AIFDEV9
802 res = -1;
803#endif
804 } else { /* PIO transfers. */
805 stat = ata_hwport->r_control;
806 if ((res = ata_wait_busy()) < 0)
807 goto finish;
808
809 /* Transfer each PIO data block. */
810 while ((int)(--cmd_state->blkcount) != -1) {
811 if ((res = ata_pio_transfer(cmd_state)) < 0)
812 goto finish;
813 if ((res = ata_wait_busy()) < 0)
814 goto finish;
815 }
816 }
817
818 if (res)
819 goto finish;
820
821 /* Wait until the device isn't busy. */
822 if (ata_hwport->r_status & ATA_STAT_BUSY)
823 res = ata_wait_busy();
824 if ((stat = ata_hwport->r_status) & ATA_STAT_ERR) {
825 M_PRINTF("Error: Command error: status 0x%02x, error 0x%02x.\n", stat, sceAtaGetError());
826 /* In v1.04, there was no check for ICRC. */
827 res = (sceAtaGetError() & ATA_ERR_ICRC) ? ATA_RES_ERR_ICRC : ATA_RES_ERR_IO;
828 }
829
830finish:
831 /* The command has completed (with an error or not), so clean things up. */
832 CancelAlarm(&ata_alarm_cb, NULL);
833#ifdef ATA_USE_DEV9
834 /* Turn off the LED. */
835 SpdSetLED(0);
836#endif
837
838 if (res)
839 M_PRINTF("error: ATA failed, %d\n", res);
840
841 return res;
842}
843
844/* Reset the ATA controller/bus. */
845static int ata_bus_reset(void)
846{
847#ifdef ATA_USE_DEV9
848 USE_SPD_REGS;
849 SPD_REG16(SPD_R_IF_CTRL) = SPD_IF_ATA_RESET;
850 DelayThread(100);
851 SPD_REG16(SPD_R_IF_CTRL) = 0; // Not present in v1.04.
852 SPD_REG16(SPD_R_IF_CTRL) = 0x48;
853 DelayThread(3000);
854#endif
855 return ata_wait_busy();
856}
857
858/* Export 5 */
859int sceAtaSoftReset(void)
860{
861#ifdef ATA_USE_DEV9
862 USE_ATA_REGS;
863#endif
864#ifdef ATA_USE_AIFDEV9
865 USE_AIF_ATA_REGS;
866#endif
867
868 if (ata_hwport->r_control & 0x80)
869 return ATA_RES_ERR_NOTREADY;
870
871 /* Disables device interrupt assertion and asserts SRST. */
872 ata_hwport->r_control = 6;
873 DelayThread(100);
874
875 /* Disable ATA interrupts. */
876 ata_hwport->r_control = 2;
877 DelayThread(3000);
878
879 return ata_wait_busy();
880}
881
882/* Export 17 */
883int sceAtaFlushCache(int device)
884{
885 int res;
886
887 if (!(res = sceAtaExecCmd(NULL, 1, 0, 0, 0, 0, 0, (device << 4) & 0xffff, (atad_devinfo[device].lba48 && !ata_dvrp_workaround) ? ATA_C_FLUSH_CACHE_EXT : ATA_C_FLUSH_CACHE)))
888 res = sceAtaWaitResult();
889
890 return res;
891}
892
893/* Export 13 */
894int sceAtaIdle(int device, int period)
895{
896 int res;
897
898 if (!(res = sceAtaExecCmd(NULL, 1, 0, period & 0xff, 0, 0, 0, (device << 4) & 0xffff, ATA_C_IDLE)))
899 res = sceAtaWaitResult();
900
901 return res;
902}
903
904static int ata_device_identify(int device, void *info)
905{
906 int res;
907
908 if (!(res = sceAtaExecCmd(info, 1, 0, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_IDENTIFY_DEVICE)))
909 res = sceAtaWaitResult();
910
911 return res;
912}
913
914static int ata_device_pkt_identify(int device, void *info)
915{
916 int res;
917
918 res = sceAtaExecCmd(info, 1, 0, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_IDENTIFY_PACKET_DEVICE);
919 if (!res)
920 return sceAtaWaitResult();
921 return res;
922}
923
924/* Export 14 */
925int sceAtaGetSceId(int device, void *data)
926{
927 int res;
928
929 if (!(res = sceAtaExecCmd(data, 1, ATA_SCE_IDENTIFY_DRIVE, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL)))
930 res = sceAtaWaitResult();
931
932 return res;
933}
934
935static int ata_device_smart_enable(int device)
936{
937 int res;
938
939 if (!(res = sceAtaExecCmd(NULL, 1, ATA_S_SMART_ENABLE_OPERATIONS, 0, 0, 0x4f, 0xc2, (device << 4) & 0xffff, ATA_C_SMART)))
940 res = sceAtaWaitResult();
941
942 return res;
943}
944
945/* Export 16 */
946int sceAtaSmartSaveAttr(int device)
947{
948 int res;
949
950 if (!(res = sceAtaExecCmd(NULL, 1, ATA_S_SMART_SAVE_ATTRIBUTE_VALUES, 0, 0, 0x4f, 0xc2, (device << 4) & 0xffff, ATA_C_SMART)))
951 res = sceAtaWaitResult();
952
953 return res;
954}
955
956/* Export 15 */
957int sceAtaSmartReturnStatus(int device)
958{
959 USE_ATA_REGS;
960 int res;
961
962 res = sceAtaExecCmd(NULL, 1, ATA_S_SMART_RETURN_STATUS, 0, 0, 0x4f, 0xc2, (device << 4) & 0xffff, ATA_C_SMART);
963 if (res)
964 return res;
965
966 res = sceAtaWaitResult();
967 if (res)
968 return res;
969
970 /* Check to see if the report exceeded the threshold. */
971 if (((ata_hwport->r_lcyl & 0xFF) != 0x4f) || ((ata_hwport->r_hcyl & 0xFF) != 0xc2)) {
972 M_PRINTF("Error: SMART report exceeded threshold.\n");
973 return 1;
974 }
975
976 return 0;
977}
978
979/* Set features - set transfer mode. */
980static int ata_device_set_transfer_mode(int device, int type, int mode)
981{
982 int res;
983
984 res = sceAtaExecCmd(NULL, 1, 3, (type | mode) & 0xff, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SET_FEATURES);
985 if (res)
986 return res;
987
988 res = sceAtaWaitResult();
989 if (res)
990 return res;
991
992 switch (type) {
993#ifdef ATA_USE_DEV9
994#ifdef ATA_MWDMA_MODES
995 case ATA_XFER_MODE_MDMA:
996 ata_multiword_dma_mode(mode);
997 break;
998#endif
999 case ATA_XFER_MODE_UDMA:
1000 ata_ultra_dma_mode(mode);
1001 break;
1002 case ATA_XFER_MODE_PIO:
1003 ata_pio_mode(mode);
1004 break;
1005#endif
1006#ifdef ATA_USE_AIFDEV9
1007 case ATA_XFER_MODE_PIO:
1008 aif_tune_drive(0, mode);
1009 break;
1010#endif
1011 }
1012
1013 return 0;
1014}
1015
1016/* Export 9 */
1017/* Note: this can only support DMA modes, due to the commands issued. */
1018int sceAtaDmaTransfer(int device, void *buf, u32 lba, u32 nsectors, int dir)
1019{
1020 return ata_device_sector_io64(device, buf, (u64)lba, nsectors, dir);
1021}
1022
1023int ata_device_sector_io64(int device, void *buf, u64 lba, u32 nsectors, int dir)
1024{
1025 USE_SPD_REGS;
1026 int res = 0, retries;
1027 u16 sector, lcyl, hcyl, select, command, len;
1028
1029 while (res == 0 && nsectors > 0) {
1030
1031 if (atad_devinfo[device].lba48 && (ata_dvrp_workaround ? (lba >= atad_devinfo[device].total_sectors) : 1)) {
1032 /* Setup for 48-bit LBA. */
1033 len = (nsectors > 65536) ? 65536 : nsectors;
1034
1035 /* Combine bits 24-31 and bits 0-7 of lba into sector. */
1036 sector = ((lba >> 16) & 0xff00) | (lba & 0xff);
1037 lcyl = ((lba >> 24) & 0xff00) | ((lba >> 8) & 0xff);
1038 hcyl = ((lba >> 32) & 0xff00) | ((lba >> 16) & 0xff);
1039
1040 /* In v1.04, LBA was enabled here. */
1041 select = (device << 4) & 0xffff;
1042 command = (dir == 1) ? ATA_C_WRITE_DMA_EXT : ATA_C_READ_DMA_EXT;
1043 } else {
1044 /* Setup for 28-bit LBA. */
1045 len = (nsectors > 256) ? 256 : nsectors;
1046 sector = lba & 0xff;
1047 lcyl = (lba >> 8) & 0xff;
1048 hcyl = (lba >> 16) & 0xff;
1049
1050 /* In v1.04, LBA was enabled here. */
1051 select = ((device << 4) | ((lba >> 24) & 0xf)) & 0xffff;
1052 command = (dir == 1) ? ATA_C_WRITE_DMA : ATA_C_READ_DMA;
1053 }
1054
1055 for (retries = 3; retries > 0; retries--) {
1056#ifdef ATA_USE_DEV9
1057#ifdef ATA_GAMESTAR_WORKAROUND
1058 /* Due to the retry loop, put this call (for the GameStar workaround) here instead of the old location. */
1059 if (ata_gamestar_workaround)
1060 ata_set_dir(dir);
1061#endif
1062#endif
1063
1064 if ((res = sceAtaExecCmd(buf, len, 0, len, sector, lcyl, hcyl, select, command)) != 0)
1065 break;
1066
1067#ifdef ATA_USE_DEV9
1068#ifdef ATA_GAMESTAR_WORKAROUND
1069 if (!ata_gamestar_workaround)
1070 ata_set_dir(dir);
1071#else
1072 /* Set up (part of) the transfer here. In v1.04, this was called at the top of the outer loop. */
1073 ata_set_dir(dir);
1074#endif
1075#endif
1076
1077 res = sceAtaWaitResult();
1078
1079 /* In v1.04, this was not done. Neither was there a mechanism to retry if a non-permanent error occurs. */
1080 SPD_REG16(SPD_R_IF_CTRL) &= ~SPD_IF_DMA_ENABLE;
1081
1082 if (res != ATA_RES_ERR_ICRC)
1083 break;
1084 }
1085
1086 buf = (void *)((u8 *)buf + len * 512);
1087 lba += len;
1088 nsectors -= len;
1089 }
1090
1091 return res;
1092}
1093
1094static void ata_get_security_status(int device, ata_devinfo_t *devinfo, u16 *param)
1095{
1096 if (ata_device_identify(device, param) == 0)
1097 devinfo[device].security_status = param[ATA_ID_SECURITY_STATUS];
1098}
1099
1100/* Export 10 */
1101int sceAtaSecuritySetPassword(int device, void *password)
1102{
1103 ata_devinfo_t *devinfo = atad_devinfo;
1104 u16 *param = ata_param;
1105 int res;
1106
1107 if (devinfo[device].security_status & ATA_F_SEC_ENABLED)
1108 return 0;
1109
1110 memset(param, 0, 512);
1111 memcpy(param + 1, password, 32);
1112
1113 res = sceAtaExecCmd(param, 1, ATA_SCE_SECURITY_SET_PASSWORD, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL);
1114 if (res == 0)
1115 res = sceAtaWaitResult();
1116
1117 ata_get_security_status(device, devinfo, param);
1118 return res;
1119}
1120
1121/* Export 11 */
1122int sceAtaSecurityUnLock(int device, void *password)
1123{
1124 ata_devinfo_t *devinfo = atad_devinfo;
1125 u16 *param = ata_param;
1126 int res;
1127
1128 if (!(devinfo[device].security_status & ATA_F_SEC_LOCKED))
1129 return 0;
1130
1131 memset(param, 0, 512);
1132 memcpy(param + 1, password, 32);
1133
1134 if ((res = sceAtaExecCmd(param, 1, ATA_SCE_SECURITY_UNLOCK, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL)) != 0)
1135 return res;
1136 if ((res = sceAtaWaitResult()) != 0)
1137 return res;
1138
1139 /* Check to see if the drive was actually unlocked. */
1140 ata_get_security_status(device, devinfo, param);
1141 if (devinfo[device].security_status & ATA_F_SEC_LOCKED)
1142 return ATA_RES_ERR_LOCKED;
1143
1144 return 0;
1145}
1146
1147/* Export 12 */
1148int sceAtaSecurityEraseUnit(int device)
1149{
1150 ata_devinfo_t *devinfo = atad_devinfo;
1151 int res;
1152
1153 if (!(devinfo[device].security_status & ATA_F_SEC_ENABLED) || !(devinfo[device].security_status & ATA_F_SEC_LOCKED))
1154 return 0;
1155
1156 /* First send the mandatory ERASE PREPARE command. */
1157 if ((res = sceAtaExecCmd(NULL, 1, ATA_SCE_SECURITY_ERASE_PREPARE, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL)) != 0)
1158 goto finish;
1159 if ((res = sceAtaWaitResult()) != 0)
1160 goto finish;
1161
1162 if ((res = sceAtaExecCmd(NULL, 1, ATA_SCE_SECURITY_ERASE_UNIT, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL)) == 0)
1163 res = sceAtaWaitResult();
1164
1165finish:
1166 ata_get_security_status(device, devinfo, NULL);
1167 return res;
1168}
1169
1170static void ata_device_probe(ata_devinfo_t *devinfo)
1171{
1172#ifdef ATA_USE_DEV9
1173 USE_ATA_REGS;
1174#endif
1175#ifdef ATA_USE_AIFDEV9
1176 USE_AIF_ATA_REGS;
1177#endif
1178 u16 nsector, sector, lcyl, hcyl;
1179
1180 devinfo->exists = 0;
1181 devinfo->has_packet = 2;
1182
1183 if (ata_hwport->r_control & 0x88)
1184 return;
1185
1186 nsector = ata_hwport->r_nsector & 0xff;
1187 sector = ata_hwport->r_sector & 0xff;
1188 lcyl = ata_hwport->r_lcyl & 0xff;
1189 hcyl = ata_hwport->r_hcyl & 0xff;
1190 (void)ata_hwport->r_select;
1191
1192 if ((nsector != 1) || (sector != 1))
1193 return;
1194 devinfo->exists = 1;
1195
1196 if ((lcyl == 0x00) && (hcyl == 0x00))
1197 devinfo->has_packet = 0;
1198 else if ((lcyl == 0x14) && (hcyl == 0xeb))
1199 devinfo->has_packet = 1;
1200
1201 /* Seems to be for ensuring that there is a device connected.
1202 Not sure why this has to be done, but is present in v2.4. */
1203 ata_hwport->r_lcyl = 0x55;
1204 ata_hwport->r_hcyl = 0xaa;
1205 lcyl = ata_hwport->r_lcyl & 0xff;
1206 hcyl = ata_hwport->r_hcyl & 0xff;
1207
1208 if ((lcyl != 0x55) || (hcyl != 0xaa))
1209 devinfo->exists = 0;
1210}
1211
1212static int ata_init_devices(ata_devinfo_t *devinfo)
1213{
1214#ifdef ATA_USE_DEV9
1215 USE_ATA_REGS;
1216#endif
1217#ifdef ATA_USE_AIFDEV9
1218 USE_AIF_ATA_REGS;
1219#endif
1220 int i, res;
1221 u32 total_sectors_nonlba48, total_sectors_lba48;
1222
1223 if ((res = sceAtaSoftReset()) != 0)
1224 return res;
1225
1226 ata_device_probe(&devinfo[0]);
1227 if (!devinfo[0].exists) {
1228 M_PRINTF("Error: Unable to detect HDD 0.\n");
1229 devinfo[1].exists = 0;
1230 return ATA_RES_ERR_NODEV; // Returns 0 in v1.04.
1231 }
1232
1233 /* If there is a device 1, grab it's info too. */
1234 if ((res = ata_device_select(1)) != 0)
1235 return res;
1236 if (ata_hwport->r_control & 0xff)
1237 ata_device_probe(&devinfo[1]);
1238 else
1239 devinfo[1].exists = 0;
1240
1241#ifdef ATA_USE_DEV9
1242 ata_pio_mode(0); // PIO mode is set here, in late ATAD versions.
1243#endif
1244
1245 for (i = 0; i < 2; i++) {
1246 if (!devinfo[i].exists)
1247 continue;
1248
1249 /* Send the IDENTIFY DEVICE command. if it doesn't succeed
1250 devinfo is disabled. */
1251 if (!devinfo[i].has_packet) {
1252 res = ata_device_identify(i, ata_param);
1253 devinfo[i].exists = (res == 0);
1254 } else if (devinfo[i].has_packet == 1) {
1255 /* If it's a packet device, send the IDENTIFY PACKET
1256 DEVICE command. */
1257 res = ata_device_pkt_identify(i, ata_param);
1258 devinfo[i].exists = (res == 0);
1259 }
1260 /* Otherwise, do nothing if has_packet = 2. */
1261
1262 /* This next section is HDD-specific: if no device or it's a
1263 packet (ATAPI) device, we're done. */
1264 if (!devinfo[i].exists || devinfo[i].has_packet)
1265 continue;
1266
1267 /* This section is to detect whether the HDD supports 48-bit LBA
1268 (IDENITFY DEVICE bit 10 word 83) and get the total sectors from
1269 either words(61:60) for 28-bit or words(103:100) for 48-bit. */
1270 devinfo[i].lba48 = (ata_param[ATA_ID_COMMAND_SETS_SUPPORTED] & 0x0400) != 0;
1271
1272 /* Save the total sector counts before we overwrite ata_param with the value of Sony identify drive command. */
1273 total_sectors_nonlba48 = (ata_param[ATA_ID_SECTOTAL_HI] << 16) | ata_param[ATA_ID_SECTOTAL_LO];
1274 if (ata_param[ATA_ID_48BIT_SECTOTAL_HI]) {
1275 total_sectors_lba48 = 0xffffffff;
1276 } else {
1277 total_sectors_lba48 = (ata_param[ATA_ID_48BIT_SECTOTAL_MI] << 16) | ata_param[ATA_ID_48BIT_SECTOTAL_LO];
1278 }
1279
1280 devinfo[i].security_status = ata_param[ATA_ID_SECURITY_STATUS];
1281
1282#ifdef ATA_USE_DEV9
1283 u8 maxUDMA = 4;
1284#ifdef ATA_ENABLE_MAXUDMA
1285 maxUDMA = 6;
1286#endif
1287
1288 /* Ultra DMA mode 4. */
1289 u8 udmaMode = 4;
1290 /* Check the highest UDMA mode supported */
1291 for (int j = maxUDMA; j >= 0; j--) {
1292 /* Check if the current UDMA mode is supported, store it and exit from the loop. */
1293 if (((ata_param[ATA_ID_UDMA_CONTROL] & 0xFF) & (1 << j)) != 0) {
1294 udmaMode = j;
1295 break;
1296 }
1297 }
1298 ata_device_set_transfer_mode(i, ATA_XFER_MODE_UDMA, udmaMode);
1299#endif
1300#ifdef ATA_USE_AIFDEV9
1301 /* PIO mode 4. */
1302 ata_device_set_transfer_mode(i, ATA_XFER_MODE_PIO, 4);
1303#endif
1304 ata_device_smart_enable(i);
1305 /* Set standby timer to 21min 15s. */
1306 sceAtaIdle(i, 0xff);
1307
1308 if (devinfo[i].lba48) {
1309 /* If this device is emulated through the DVRP, use the non-48-bit LBA size. */
1310 if (ata_dvrp_workaround) {
1311 devinfo[i].total_sectors = total_sectors_nonlba48;
1312 } else {
1313 devinfo[i].total_sectors = total_sectors_lba48;
1314 }
1315 devinfo[i].total_sectors_lba48 = total_sectors_lba48;
1316 } else {
1317 devinfo[i].total_sectors = total_sectors_nonlba48;
1318 devinfo[i].total_sectors_lba48 = total_sectors_nonlba48;
1319 }
1320
1321 /* Call the proprietary identify command. */
1322#ifdef ATA_SCE_AUTH_HDD
1323 if (sceAtaGetSceId(i, ata_param) != 0) {
1324 M_PRINTF("error: This is not SCE genuine HDD.\n");
1325 memset(&devinfo[i], 0, sizeof(devinfo[i]));
1326 }
1327#endif
1328
1329#ifdef ATA_ENABLE_BDM
1330 g_ata_bd[i].sectorCount = devinfo[i].total_sectors_lba48;
1331 bdm_connect_bd(&g_ata_bd[i]);
1332#endif
1333 }
1334 return 0;
1335}
1336
1337/* Export 4 */
1338ata_devinfo_t *sceAtaInit(int device)
1339{
1340 if (!ata_devinfo_init) {
1341 ata_devinfo_init = 1;
1342 if (ata_bus_reset() || ata_init_devices(atad_devinfo))
1343 return NULL;
1344 }
1345
1346 return &atad_devinfo[device];
1347}
1348
1349#ifdef ATA_USE_DEV9
1350static void ata_set_dir(int dir)
1351{
1352 USE_SPD_REGS;
1353 u16 val;
1354
1355 SPD_REG16(0x38) = 3;
1356 val = SPD_REG16(SPD_R_IF_CTRL) & 1;
1357 val |= (dir == ATA_DIR_WRITE) ? 0x4c : 0x4e;
1358 SPD_REG16(SPD_R_IF_CTRL) = val;
1359#ifdef ATA_GAMESTAR_WORKAROUND
1360 SPD_REG16(SPD_R_XFR_CTRL) = dir | (ata_gamestar_workaround ? 0x86 : 0x6);
1361#else
1362 SPD_REG16(SPD_R_XFR_CTRL) = dir | 0x6; // In v1.04, DMA was enabled here (0x86 instead of 0x6)
1363#endif
1364}
1365
1366static void ata_pio_mode(int mode)
1367{
1368 USE_SPD_REGS;
1369 (void)mode;
1370#ifdef ATA_ALL_PIO_MODES
1371 u16 val;
1372
1373 switch (mode) {
1374 case 1:
1375 val = 0x72;
1376 break;
1377 case 2:
1378 val = 0x32;
1379 break;
1380 case 3:
1381 val = 0x24;
1382 break;
1383 case 4:
1384 val = 0x23;
1385 break;
1386 default:
1387 val = 0x92;
1388 }
1389
1390 SPD_REG16(SPD_R_PIO_MODE) = val;
1391#else
1392 /* In the late ATAD versions, PIO mode 0 is always used if PIO mode is utilized. */
1393 SPD_REG16(SPD_R_PIO_MODE) = 0x92;
1394#endif
1395}
1396
1397#ifdef ATA_MWDMA_MODES
1398static void ata_multiword_dma_mode(int mode)
1399{
1400 USE_SPD_REGS;
1401 u16 val;
1402
1403 switch (mode) {
1404 case 1:
1405 val = 0x45;
1406 break;
1407 case 2:
1408 val = 0x24;
1409 break;
1410 default:
1411 val = 0xff;
1412 }
1413
1414 SPD_REG16(SPD_R_MWDMA_MODE) = val;
1415 SPD_REG16(SPD_R_IF_CTRL) = (SPD_REG16(SPD_R_IF_CTRL) & 0xfffe) | 0x48;
1416}
1417#endif
1418
1419static void ata_ultra_dma_mode(int mode)
1420{
1421 USE_SPD_REGS;
1422 u16 val;
1423
1424 switch (mode) {
1425 case 1:
1426 val = 0x85;
1427 break;
1428 case 2:
1429 val = 0x63;
1430 break;
1431 case 3:
1432 val = 0x62;
1433 break;
1434 case 4:
1435 val = 0x61;
1436 break;
1437 default:
1438 val = 0xa7;
1439 }
1440
1441 SPD_REG16(SPD_R_UDMA_MODE) = val;
1442 SPD_REG16(SPD_R_IF_CTRL) |= 0x49;
1443}
1444#endif
1445
1446#ifdef ATA_USE_AIFDEV9
1447static void aif_tune_drive(int unit, int mode)
1448{
1449 USE_AIF_REGS;
1450 unsigned int use_iordy, value;
1451
1452 use_iordy = 1;
1453 value = (use_iordy << 3) | mode;
1454 M_PRINTF("AIF HDD: tune unit%d, mode=%u\n", unit, value);
1455
1456 switch (unit) {
1457 case 0:
1458 aif_regs[AIF_ATA_TCFG] = (aif_regs[AIF_ATA_TCFG] & 0xf0) + value;
1459 break;
1460 case 1:
1461 aif_regs[AIF_ATA_TCFG] = (aif_regs[AIF_ATA_TCFG] & 0x0f) + (value << 4);
1462 break;
1463 }
1464}
1465#endif
1466
1467/* Export 18 */
1468int sceAtaIdleImmediate(int device)
1469{
1470 int res;
1471
1472 if (!(res = sceAtaExecCmd(NULL, 1, 0, 0, 0, 0, 0, (device << 4) & 0xFFFF, ATA_C_IDLE_IMMEDIATE)))
1473 res = sceAtaWaitResult();
1474
1475 return res;
1476}
1477
1478static int ata_device_standby_immediate(int device)
1479{
1480 int res;
1481
1482 if (!(res = sceAtaExecCmd(NULL, 1, 0, 0, 0, 0, 0, (device << 4) & 0xFFFF, ATA_C_STANDBY_IMMEDIATE)))
1483 res = sceAtaWaitResult();
1484
1485 return res;
1486}
1487
1488static void ata_shutdown_cb(void)
1489{
1490 int i;
1491
1492 for (i = 0; i < 2; i++) {
1493 if (atad_devinfo[i].exists)
1494 ata_device_standby_immediate(i);
1495 }
1496}
1497
1498#ifdef ATA_ENABLE_BDM
1499//
1500// Block device interface
1501//
1502static int ata_bd_read(struct block_device *bd, u64 sector, void *buffer, u16 count)
1503{
1504 if (ata_device_sector_io64(bd->devNr, buffer, sector, count, ATA_DIR_READ) != 0) {
1505 return -EIO;
1506 }
1507
1508 return count;
1509}
1510
1511static int ata_bd_write(struct block_device *bd, u64 sector, const void *buffer, u16 count)
1512{
1513 if (ata_device_sector_io64(bd->devNr, (void *)buffer, sector, count, ATA_DIR_WRITE) != 0) {
1514 return -EIO;
1515 }
1516
1517 return count;
1518}
1519
1520static void ata_bd_flush(struct block_device *bd)
1521{
1522 sceAtaFlushCache(bd->devNr);
1523}
1524
1525static int ata_bd_stop(struct block_device *bd)
1526{
1527 ata_device_standby_immediate(bd->devNr);
1528
1529 return 0;
1530}
1531#endif
_ata_devinfo::security_status
u32 security_status
Definition atad.h:35
_ata_devinfo::lba48
u32 lba48
Definition atad.h:37
_ata_devinfo::exists
s32 exists
Definition atad.h:29
_ata_devinfo::total_sectors
u32 total_sectors
Definition atad.h:33
_ata_devinfo::has_packet
s32 has_packet
Definition atad.h:31
_ata_devinfo::total_sectors_lba48
u32 total_sectors_lba48
Definition atad.h:39
_ata_devinfo
Definition atad.h:27
block_device
Definition bdm.h:22
EIO
#define EIO
Definition errno.h:29
irx_export_table
Definition irx.h:90
_ata_cmd_info
Definition ps2atad.c:88
_ata_cmd_state
Definition ps2atad.c:177
s_info
Definition xprintf.c:78
_iop_sys_clock
Definition thbase.h:88
EA_SINGLE
#define EA_SINGLE
Definition thevent.h:33
iop_event_t
Definition thevent.h:38
count
u32 count
start sector of fragmented bd/file
Definition usbhdfsd-common.h:1