PS2SDK
PS2 Homebrew Libraries
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ps2atad.c
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1/*
2# _____ ___ ____ ___ ____
3# ____| | ____| | | |____|
4# | ___| |____ ___| ____| | \ PS2DEV Open Source Project.
5#-----------------------------------------------------------------------
6# Copyright (c) 2003 Marcus R. Brown <mrbrown@0xd6.org>
7# Licenced under Academic Free License version 2.0
8# Review ps2sdk README & LICENSE files for further details.
9*/
10
22#include <types.h>
23#include <defs.h>
24#include <irx.h>
25#include <loadcore.h>
26#include <thbase.h>
27#include <thevent.h>
28#include <stdio.h>
29#include <sysclib.h>
30#ifdef ATA_USE_DEV9
31#include <dev9.h>
32#endif
33#ifdef ATA_USE_AIFDEV9
34#include <aifdev9.h>
35#endif
36#include <atad.h>
37#ifdef ATA_ENABLE_BDM
38#include <bdm.h>
39#include <errno.h>
40#endif
41
42#ifdef ATA_USE_DEV9
43#include <speedregs.h>
44#endif
45#include <atahw.h>
46
47#define MODNAME "atad"
48// TODO: last sdk 3.1.0 has ATAD module version 2.9 with significant changes.
49// Check what was changed, and maybe port changes.
50// CRC32: C2337807
51IRX_ID(MODNAME, 2, 7);
52
53#define M_PRINTF(format, args...) \
54 printf(MODNAME ": " format, ##args)
55
56#define BANNER "ATA device driver %s - Copyright (c) 2003 Marcus R. Brown\n"
57#define VERSION "v1.2"
58
59#define ATA_XFER_MODE_PIO 0x08
60#ifdef ATA_MWDMA_MODES
61#define ATA_XFER_MODE_MDMA 0x20
62#endif
63#define ATA_XFER_MODE_UDMA 0x40
64
65#define ATA_EV_TIMEOUT 1
66#define ATA_EV_COMPLETE 2
67
68static int ata_devinfo_init = 0;
69static int ata_evflg = -1;
70
71// Workarounds
72static u8 ata_dvrp_workaround = 0; // Please read the comments in _start().
73#ifdef ATA_USE_DEV9
74#ifdef ATA_GAMESTAR_WORKAROUND
75static u8 ata_gamestar_workaround = 0;
76#endif
77#endif
78
79/* Local device info kept for drives 0 and 1. */
80static ata_devinfo_t atad_devinfo[2];
81
82/* Data returned from DEVICE IDENTIFY is kept here. Also, this is used by the
83 security commands to set and unlock the password. */
84static u16 ata_param[256];
85
86/* ATA command info. */
87typedef struct _ata_cmd_info
88{
89 u8 command;
90 u8 type;
91} ata_cmd_info_t;
92
93static const ata_cmd_info_t ata_cmd_table[] = {
94 {ATA_C_NOP, 1},
95 {ATA_C_CFA_REQUEST_EXTENDED_ERROR_CODE, 1},
96 {ATA_C_DEVICE_RESET, 5},
97 {ATA_C_READ_SECTOR, 2},
98 {ATA_C_READ_SECTOR_EXT, 0x82},
99 {ATA_C_READ_DMA_EXT, 0x84},
100 {ATA_C_READ_NATIVE_MAX_ADDRESS_EXT, 0x81},
101 {ATA_C_READ_MULTIPLE_EXT, 0x82},
102 {ATA_C_WRITE_SECTOR, 3},
103 {ATA_C_WRITE_LONG, 8},
104 {ATA_C_WRITE_SECTOR_EXT, 0x83},
105 {ATA_C_WRITE_DMA_EXT, 0x84},
106 {ATA_C_SET_MAX_ADDRESS_EXT, 0x81},
107 {ATA_C_CFA_WRITE_SECTORS_WITHOUT_ERASE, 3},
108 {ATA_C_WRITE_MULTIPLE_EXT, 0x83},
109 {ATA_C_READ_VERIFY_SECTOR, 1},
110 {ATA_C_READ_VERIFY_SECTOR_EXT, 0x81},
111 {ATA_C_SEEK, 1},
112 {ATA_C_CFA_TRANSLATE_SECTOR, 2},
113 {ATA_C_SCE_SECURITY_CONTROL, 7},
114 {ATA_C_EXECUTE_DEVICE_DIAGNOSTIC, 6},
115 {ATA_C_INITIALIZE_DEVICE_PARAMETERS, 1},
116 {ATA_C_DOWNLOAD_MICROCODE, 3},
117 {ATA_C_IDENTIFY_PACKET_DEVICE, 2},
118 {ATA_C_SMART, 7},
119 {ATA_C_CFA_ERASE_SECTORS, 1},
120 {ATA_C_READ_MULTIPLE, 2},
121 {ATA_C_WRITE_MULTIPLE, 3},
122 {ATA_C_SET_MULTIPLE_MODE, 1},
123 {ATA_C_READ_DMA, 4},
124 {ATA_C_WRITE_DMA, 4},
125 {ATA_C_CFA_WRITE_MULTIPLE_WITHOUT_ERASE, 3},
126 {ATA_C_GET_MEDIA_STATUS, 1},
127 {ATA_C_MEDIA_LOCK, 1},
128 {ATA_C_MEDIA_UNLOCK, 1},
129 {ATA_C_STANDBY_IMMEDIATE, 1},
130 {ATA_C_IDLE_IMMEDIATE, 1},
131 {ATA_C_STANDBY, 1},
132 {ATA_C_IDLE, 1},
133 {ATA_C_READ_BUFFER, 2},
134 {ATA_C_CHECK_POWER_MODE, 1},
135 {ATA_C_SLEEP, 1},
136 {ATA_C_FLUSH_CACHE, 1},
137 {ATA_C_WRITE_BUFFER, 3},
138 {ATA_C_FLUSH_CACHE_EXT, 1},
139 {ATA_C_IDENTIFY_DEVICE, 2},
140 {ATA_C_MEDIA_EJECT, 1},
141 {ATA_C_SET_FEATURES, 1},
142 {ATA_C_SECURITY_SET_PASSWORD, 3},
143 {ATA_C_SECURITY_UNLOCK, 3},
144 {ATA_C_SECURITY_ERASE_PREPARE, 1},
145 {ATA_C_SECURITY_ERASE_UNIT, 3},
146 {ATA_C_SECURITY_FREEZE_LOCK, 1},
147 {ATA_C_SECURITY_DISABLE_PASSWORD, 3},
148 {ATA_C_READ_NATIVE_MAX_ADDRESS, 1},
149 {ATA_C_SET_MAX_ADDRESS, 1}};
150#define ATA_CMD_TABLE_SIZE (sizeof ata_cmd_table / sizeof(ata_cmd_info_t))
151
152static const ata_cmd_info_t sec_ctrl_cmd_table[] = {
153 {ATA_SCE_IDENTIFY_DRIVE, 2},
154 {ATA_SCE_SECURITY_ERASE_PREPARE, 1},
155 {ATA_SCE_SECURITY_ERASE_UNIT, 1},
156 {ATA_SCE_SECURITY_FREEZE_LOCK, 1},
157 {ATA_SCE_SECURITY_SET_PASSWORD, 3},
158 {ATA_SCE_SECURITY_UNLOCK, 3},
159 {ATA_SCE_SECURITY_WRITE_ID, 3},
160 {ATA_SCE_SECURITY_READ_ID, 2}};
161#define SEC_CTRL_CMD_TABLE_SIZE (sizeof sec_ctrl_cmd_table / sizeof(ata_cmd_info_t))
162
163static const ata_cmd_info_t smart_cmd_table[] = {
164 {ATA_S_SMART_READ_DATA, 2},
165 {ATA_S_SMART_ENABLE_DISABLE_AUTOSAVE, 1},
166 {ATA_S_SMART_SAVE_ATTRIBUTE_VALUES, 1},
167 {ATA_S_SMART_EXECUTE_OFF_LINE, 1},
168 {ATA_S_SMART_READ_LOG, 2},
169 {ATA_S_SMART_WRITE_LOG, 3},
170 {ATA_S_SMART_ENABLE_OPERATIONS, 1},
171 {ATA_S_SMART_DISABLE_OPERATIONS, 1},
172 {ATA_S_SMART_RETURN_STATUS, 1}};
173#define SMART_CMD_TABLE_SIZE (sizeof smart_cmd_table / sizeof(ata_cmd_info_t))
174
175/* This is the state info tracked between sceAtaExecCmd() and sceAtaWaitResult(). */
176typedef struct _ata_cmd_state
177{
178 s32 type; /* The ata_cmd_info_t type field. */
179 union
180 {
181 void *buf;
182 u8 *buf8;
183 u16 *buf16;
184 };
185 u32 blkcount; /* The number of 512-byte blocks (sectors) to transfer. */
186 s32 dir; /* DMA direction: 0 - to RAM, 1 - from RAM. */
187} ata_cmd_state_t;
188
189static ata_cmd_state_t atad_cmd_state;
190
191#ifdef ATA_ENABLE_BDM
192#define NUM_DEVICES 2
193#define ATA_BD_SECTOR_SIZE 512
194static struct block_device g_ata_bd[NUM_DEVICES];
195#endif
196
197#ifdef ATA_USE_DEV9
198static int ata_intr_cb(int flag);
199#endif
200#ifdef ATA_USE_AIFDEV9
201static int ata_intr_cb(void);
202#endif
203static unsigned int ata_alarm_cb(void *unused);
204
205#ifdef ATA_USE_AIFDEV9
206static void aif_tune_drive(int unit, int mode);
207#endif
208
209#ifdef ATA_USE_DEV9
210static void ata_set_dir(int dir);
211
212static void ata_pio_mode(int mode);
213#ifdef ATA_MWDMA_MODES
214static void ata_multiword_dma_mode(int mode);
215#endif
216static void ata_ultra_dma_mode(int mode);
217#endif
218static void ata_shutdown_cb(void);
219
220int ata_device_sector_io64(int device, void *buf, u64 lba, u32 nsectors, int dir);
221
222#ifdef ATA_ENABLE_BDM
223static int ata_bd_read(struct block_device *bd, u64 sector, void *buffer, u16 count);
224static int ata_bd_write(struct block_device *bd, u64 sector, const void *buffer, u16 count);
225static void ata_bd_flush(struct block_device *bd);
226static int ata_bd_stop(struct block_device *bd);
227#endif
228
229extern struct irx_export_table _exp_atad;
230
231#ifdef ATA_USE_DEV9
232// In v1.04, DMA was enabled in ata_set_dir() instead.
233static void ata_pre_dma_cb(int bcr, int dir)
234{
235 USE_SPD_REGS;
236
237 (void)bcr;
238 (void)dir;
239
240 SPD_REG16(SPD_R_XFR_CTRL) |= 0x80;
241}
242
243static void ata_post_dma_cb(int bcr, int dir)
244{
245 USE_SPD_REGS;
246
247 (void)bcr;
248 (void)dir;
249
250 SPD_REG16(SPD_R_XFR_CTRL) &= ~0x80;
251}
252#endif
253
254static int ata_create_event_flag(void)
255{
256 iop_event_t event;
257
258 event.attr = EA_SINGLE; // In v1.04, EA_MULTI was specified.
259 event.bits = 0;
260 return CreateEventFlag(&event);
261}
262
263int _start(int argc, char *argv[])
264{
265#ifdef ATA_USE_DEV9
266 USE_SPD_REGS;
267#endif
268#ifdef ATA_USE_AIFDEV9
269 USE_AIF_REGS;
270#endif
271 int res;
272
273 (void)argc;
274 (void)argv;
275
276 printf(BANNER, VERSION);
277
278 res = MODULE_NO_RESIDENT_END;
279
280#ifdef ATA_USE_DEV9
281 if (!(SPD_REG16(SPD_R_REV_3) & SPD_CAPS_ATA) || !(SPD_REG16(SPD_R_REV_8) & 0x02)) {
282 M_PRINTF("HDD is not connected, exiting.\n");
283 goto out;
284 }
285
286 /* The PSX (Not the PlayStation or PSOne, but a PS2 with a DVR unit) has got an extra processor (Fujitsu MB91302A, aka the "DVRP") that seems to be emulating the console's PS2 ATA interface.
287 The stock disks of all PSX units are definitely 48-bit LBA compliant because of their capacities, but the DVRP's emulation seems to have a design problem:
288 1. It indicates that 48-bit LBA is supported.
289 2. The 48-bit LBA capacity fields show the true capacity of the disk.
290 3. Accesses to beyond the 28-bit LBA capacity (Which is 40.000GB by default) will result in I/O errors.
291 4. (For some PSX units like the DESR-7500): Double-writes to the ATA registers seem to cause the ATA interface to stall.
292
293 The problem is obviously in the DVRP's firmware, but we currently have no way to fix these bugs because the DVRP is even more heavily secured that the IOP.
294 In the eyes of Sony, there isn't a problem because none of their retail PlayStation 2 software ever supported 48-bit LBA.
295
296 The workaround here is to return the 28-bit LBA as the total size and only use 48-bit LBA commands when required. */
297 ata_dvrp_workaround = (SPD_REG16(SPD_R_REV_3) & SPD_CAPS_DVR) ? 1 : 0;
298#endif
299
300#ifdef ATA_USE_AIFDEV9
301 if (!aifIsDetected()) {
302 M_PRINTF("AIF HDD: controller not found.\n");
303 goto out;
304 }
305 aif_regs[AIF_ATA_TCFG] = 0; // Clear ATA timing configuration.
306#endif
307
308#ifdef ATA_USE_DEV9
309#ifdef ATA_GAMESTAR_WORKAROUND
310 /* Some compatible adaptors may malfunction if transfers are not done according to the old ps2atad design.
311 Official adaptors appear to have a 0x0001 set for this register, but not compatibles.
312 While official I/O to this register are 8-bit, some compatibles have a 0x01 for the lower 8-bits,
313 but the upper 8-bits contain some random value. Hence perform a 16-bit read instead. */
314 if (SPD_REG16(0x20) != 1) {
315 ata_gamestar_workaround = 1;
316 M_PRINTF("Compatible adaptor detected.\n");
317 } else {
318 ata_gamestar_workaround = 0;
319 }
320#endif
321#endif
322
323 if ((ata_evflg = ata_create_event_flag()) < 0) {
324 M_PRINTF("Couldn't create event flag, exiting.\n");
325 goto out;
326 }
327
328#ifdef ATA_USE_DEV9
329 /* In v1.04, PIO mode 0 was set here. In late versions, it is set in ata_init_devices(). */
330 SpdRegisterIntrHandler(1, &ata_intr_cb);
331 SpdRegisterIntrHandler(0, &ata_intr_cb);
332#ifdef ATA_GAMESTAR_WORKAROUND
333 if (!ata_gamestar_workaround) {
334#endif
335 dev9RegisterPreDmaCb(0, &ata_pre_dma_cb);
336 dev9RegisterPostDmaCb(0, &ata_post_dma_cb);
337#ifdef ATA_GAMESTAR_WORKAROUND
338 }
339#endif
340 /* Register this at the last position, as it should be the last thing done before shutdown. */
341 Dev9RegisterPowerOffHandler(15, &ata_shutdown_cb);
342#endif
343
344#ifdef ATA_USE_AIFDEV9
345 aifRegisterIntrCb(AIF_INUM_ATA0, &ata_intr_cb);
346 aifRegisterShutdownCb(AIF_INUM_ATA0, &ata_shutdown_cb);
347
348 M_PRINTF("AIF HDD initialized.\n");
349#endif
350
351#ifdef ATA_ENABLE_BDM
352 {
353 int i;
354
355 for (i = 0; i < NUM_DEVICES; ++i) {
356 g_ata_bd[i].priv = (void *)&atad_devinfo[i];
357 g_ata_bd[i].name = "ata";
358 g_ata_bd[i].path = "ata";
359 g_ata_bd[i].devNr = i;
360 g_ata_bd[i].parNr = 0;
361 g_ata_bd[i].parId = 0x00;
362 g_ata_bd[i].sectorSize = 512;
363 g_ata_bd[i].sectorOffset = 0;
364 g_ata_bd[i].sectorCount = 0;
365
366 g_ata_bd[i].read = ata_bd_read;
367 g_ata_bd[i].write = ata_bd_write;
368 g_ata_bd[i].flush = ata_bd_flush;
369 g_ata_bd[i].stop = ata_bd_stop;
370 }
371 }
372
373 sceAtaInit(0);
374 sceAtaInit(1);
375#endif
376
377 if (RegisterLibraryEntries(&_exp_atad) != 0) {
378 M_PRINTF("Library is already registered, exiting.\n");
379 goto out;
380 }
381
382 res = MODULE_RESIDENT_END;
383 M_PRINTF("Driver loaded.\n");
384out:
385 return res;
386}
387
388int _exit(void) { return MODULE_RESIDENT_END; }
389
390#ifdef ATA_USE_DEV9
391static int ata_intr_cb(int flag)
392{
393 if (flag == 1) { /* New card, invalidate device info. */
394 memset(atad_devinfo, 0, sizeof atad_devinfo);
395 } else {
396 SpdIntrDisable(SPD_INTR_ATA);
397 iSetEventFlag(ata_evflg, ATA_EV_COMPLETE);
398 }
399
400 return 1;
401}
402#endif
403
404#ifdef ATA_USE_AIFDEV9
405static int ata_intr_cb(void)
406{
407 aifIntrDisable(AIF_INTR_ATA0);
408 iSetEventFlag(ata_evflg, ATA_EV_COMPLETE);
409
410 return 1;
411}
412#endif
413
414static unsigned int ata_alarm_cb(void *unused)
415{
416 (void)unused;
417
418 iSetEventFlag(ata_evflg, ATA_EV_TIMEOUT);
419 return 0;
420}
421
422/* Export 8 */
423int sceAtaGetError(void)
424{
425#ifdef ATA_USE_DEV9
426 USE_ATA_REGS;
427#endif
428#ifdef ATA_USE_AIFDEV9
429 USE_AIF_ATA_REGS;
430#endif
431 return ata_hwport->r_error & 0xff;
432}
433
434#define ATA_WAIT_BUSY 0x80
435#define ATA_WAIT_BUSBUSY 0x88
436
437#define ata_wait_busy() gen_ata_wait_busy(ATA_WAIT_BUSY)
438#define ata_wait_bus_busy() gen_ata_wait_busy(ATA_WAIT_BUSBUSY)
439
440/* 0x80 for busy, 0x88 for bus busy.
441 In the original ATAD, the busy and bus-busy functions were separate, but similar. */
442static int gen_ata_wait_busy(int bits)
443{
444#ifdef ATA_USE_DEV9
445 USE_ATA_REGS;
446#endif
447#ifdef ATA_USE_AIFDEV9
448 USE_AIF_ATA_REGS;
449#endif
450 int i, delay;
451
452 for (i = 0; i < 80; i++) {
453 int didx;
454
455 if (!(ata_hwport->r_control & bits))
456 return 0;
457
458 didx = i / 10;
459 switch (didx) {
460 case 0:
461 continue;
462 case 1:
463 delay = 100;
464 break;
465 case 2:
466 delay = 1000;
467 break;
468 case 3:
469 delay = 10000;
470 break;
471 case 4:
472 delay = 100000;
473 break;
474 default:
475 delay = 1000000;
476 }
477
478 DelayThread(delay);
479 }
480
481 M_PRINTF("Timeout while waiting on busy (0x%02x).\n", bits);
482 return ATA_RES_ERR_TIMEOUT;
483}
484
485static int ata_device_select(int device)
486{
487#ifdef ATA_USE_DEV9
488 USE_ATA_REGS;
489#endif
490#ifdef ATA_USE_AIFDEV9
491 USE_AIF_ATA_REGS;
492#endif
493 int res;
494
495 if ((res = ata_wait_bus_busy()) < 0)
496 return res;
497
498 /* If the device was already selected, nothing to do. */
499 if (((ata_hwport->r_select >> 4) & 1) == device)
500 return 0;
501
502 /* Select the device. */
503 ata_hwport->r_select = (device & 1) << 4;
504 (void)(ata_hwport->r_control);
505 (void)(ata_hwport->r_control); // Only done once in v1.04.
506
507 return ata_wait_bus_busy();
508}
509
510/* Export 6 */
511/*
512 28-bit LBA:
513 sector (7:0) -> LBA (7:0)
514 lcyl (7:0) -> LBA (15:8)
515 hcyl (7:0) -> LBA (23:16)
516 device (3:0) -> LBA (27:24)
517
518 48-bit LBA just involves writing the upper 24 bits in the format above into each respective register on the first write pass, before writing the lower 24 bits in the 2nd write pass. The LBA bits within the device field are not used in either write pass.
519*/
520int sceAtaExecCmd(void *buf, u32 blkcount, u16 feature, u16 nsector, u16 sector, u16 lcyl, u16 hcyl, u16 select, u16 command)
521{
522#ifdef ATA_USE_DEV9
523 USE_ATA_REGS;
524#endif
525#ifdef ATA_USE_AIFDEV9
526 USE_AIF_ATA_REGS;
527#endif
528 iop_sys_clock_t cmd_timeout;
529 const ata_cmd_info_t *cmd_table;
530 int i, res, type, cmd_table_size;
531 int using_timeout, device = (select >> 4) & 1;
532 u8 searchcmd;
533
534 ClearEventFlag(ata_evflg, 0);
535
536 if (!atad_devinfo[device].exists)
537 return ATA_RES_ERR_NODEV;
538
539 if ((res = ata_device_select(device)) != 0)
540 return res;
541
542 /* For the SCE and SMART commands, we need to search on the subcommand
543 specified in the feature register. */
544 if (command == ATA_C_SCE_SECURITY_CONTROL) {
545 cmd_table = sec_ctrl_cmd_table;
546 cmd_table_size = SEC_CTRL_CMD_TABLE_SIZE;
547 searchcmd = (u8)feature;
548 } else if (command == ATA_C_SMART) {
549 cmd_table = smart_cmd_table;
550 cmd_table_size = SMART_CMD_TABLE_SIZE;
551 searchcmd = (u8)feature;
552 } else {
553 cmd_table = ata_cmd_table;
554 cmd_table_size = ATA_CMD_TABLE_SIZE;
555 searchcmd = (u8)command;
556 }
557
558 type = 0;
559 for (i = 0; i < cmd_table_size; i++) {
560 if (searchcmd == cmd_table[i].command) {
561 type = cmd_table[i].type;
562 break;
563 }
564 }
565
566 if (!(atad_cmd_state.type = type & 0x7F)) // Non-SONY: ignore the 48-bit LBA flag.
567 return ATA_RES_ERR_CMD;
568
569 atad_cmd_state.buf = buf;
570 atad_cmd_state.blkcount = blkcount;
571
572 /* Check that the device is ready if this the appropiate command. */
573 if (!(ata_hwport->r_control & 0x40)) {
574 switch (command) {
575 case ATA_C_DEVICE_RESET:
576 case ATA_C_EXECUTE_DEVICE_DIAGNOSTIC:
577 case ATA_C_INITIALIZE_DEVICE_PARAMETERS:
578 case ATA_C_PACKET:
579 case ATA_C_IDENTIFY_PACKET_DEVICE:
580 break;
581 default:
582 M_PRINTF("Error: Device %d is not ready.\n", device);
583 return ATA_RES_ERR_NOTREADY;
584 }
585 }
586
587 /* Does this command need a timeout? */
588 using_timeout = 0;
589 switch (type & 0x7F) { // Non-SONY: ignore the 48-bit LBA flag.
590 case 1:
591 case 6:
592 using_timeout = 1;
593 break;
594 case 4:
595 atad_cmd_state.dir = (command != ATA_C_READ_DMA && command != ATA_C_READ_DMA_EXT);
596 using_timeout = 1;
597 break;
598 }
599
600 if (using_timeout) {
601 cmd_timeout.lo = 0x41eb0000;
602 cmd_timeout.hi = 0;
603
604 /* SECURITY ERASE UNIT needs a bit more time. */
605 if (command == ATA_C_SCE_SECURITY_CONTROL && feature == ATA_SCE_SECURITY_ERASE_UNIT)
606 USec2SysClock(180000000, &cmd_timeout);
607
608 if ((res = SetAlarm(&cmd_timeout, &ata_alarm_cb, NULL)) < 0)
609 return res;
610 }
611
612 /* Enable the command completion interrupt. */
613 if ((type & 0x7F) == 1) {
614#ifdef ATA_USE_DEV9
615 SpdIntrEnable(SPD_INTR_ATA0);
616#endif
617#ifdef ATA_USE_AIFDEV9
618 aifIntrEnable(AIF_INTR_ATA0);
619#endif
620 }
621
622 /* Finally! We send off the ATA command with arguments. */
623 ata_hwport->r_control = (using_timeout == 0) << 1;
624
625 if (type & 0x80) { // For the sake of achieving improved performance, write the registers twice only if required! This is also required for compatibility with the buggy firmware of certain PSX units.
626 /* 48-bit LBA requires writing to the address registers twice,
627 24 bits of the LBA address is written each time.
628 Writing to registers twice does not affect 28-bit LBA since
629 only the latest data stored in address registers is used. */
630 ata_hwport->r_feature = (feature >> 8) & 0xff;
631 ata_hwport->r_nsector = (nsector >> 8) & 0xff;
632 ata_hwport->r_sector = (sector >> 8) & 0xff;
633 ata_hwport->r_lcyl = (lcyl >> 8) & 0xff;
634 ata_hwport->r_hcyl = (hcyl >> 8) & 0xff;
635 }
636
637 ata_hwport->r_feature = feature & 0xff;
638 ata_hwport->r_nsector = nsector & 0xff;
639 ata_hwport->r_sector = sector & 0xff;
640 ata_hwport->r_lcyl = lcyl & 0xff;
641 ata_hwport->r_hcyl = hcyl & 0xff;
642 ata_hwport->r_select = (select | ATA_SEL_LBA) & 0xff; // In v1.04, LBA was enabled in the sceAtaDmaTransfer function.
643 ata_hwport->r_command = command & 0xff;
644
645#ifdef ATA_USE_DEV9
646 /* Turn on the LED. */
647 SpdSetLED(1);
648#endif
649
650 return 0;
651}
652
653/* Do a PIO transfer, to or from the device. */
654static int ata_pio_transfer(ata_cmd_state_t *cmd_state)
655{
656#ifdef ATA_USE_DEV9
657 USE_ATA_REGS;
658#endif
659#ifdef ATA_USE_AIFDEV9
660 USE_AIF_ATA_REGS;
661#endif
662 u16 *buf16;
663 int i, type;
664 u16 status = ata_hwport->r_status & 0xff;
665
666 if (status & ATA_STAT_ERR) {
667 M_PRINTF("Error: PIO cmd error: status 0x%02x, error 0x%02x.\n", status, sceAtaGetError());
668 return ATA_RES_ERR_IO;
669 }
670
671 /* DRQ must be set (data request). */
672 if (!(status & ATA_STAT_DRQ))
673 return ATA_RES_ERR_NODATA;
674
675 type = cmd_state->type;
676
677 if (type == 3 || type == 8) {
678 /* PIO data out */
679 buf16 = cmd_state->buf16;
680 for (i = 0; i < 256; i++) {
681 ata_hwport->r_data = *buf16;
682 cmd_state->buf16 = ++buf16;
683 }
684 if (cmd_state->type == 8) {
685 u8 *buf8;
686
687 buf8 = cmd_state->buf8;
688 for (i = 0; i < 4; i++) {
689 ata_hwport->r_data = *buf8;
690 cmd_state->buf8 = ++buf8;
691 }
692 }
693 } else if (type == 2) {
694 /* PIO data in */
695 buf16 = cmd_state->buf16;
696 for (i = 0; i < 256; i++) {
697 *buf16 = ata_hwport->r_data;
698 cmd_state->buf16 = ++buf16;
699 }
700 }
701
702 return 0;
703}
704
705#ifdef ATA_USE_DEV9
706/* Complete a DMA transfer, to or from the device. */
707static int ata_dma_complete(void *buf, u32 blkcount, int dir)
708{
709 USE_ATA_REGS;
710 USE_SPD_REGS;
711 u32 bits, count, nbytes;
712 int i, res;
713 u16 dma_stat;
714
715 while (blkcount) {
716 for (i = 0; i < 20; i++)
717 if ((dma_stat = SPD_REG16(0x38) & 0x1f))
718 goto next_transfer;
719
720 if (dma_stat)
721 goto next_transfer;
722
723 SpdIntrEnable(SPD_INTR_ATA);
724 /* Wait for the previous transfer to complete or a timeout. */
725 WaitEventFlag(ata_evflg, ATA_EV_TIMEOUT | ATA_EV_COMPLETE, WEF_CLEAR | WEF_OR, &bits);
726
727 if (bits & ATA_EV_TIMEOUT) { /* Timeout. */
728 M_PRINTF("Error: DMA timeout.\n");
729 return ATA_RES_ERR_TIMEOUT;
730 }
731 /* No DMA completion bit? Spurious interrupt. */
732 if (!(SPD_REG16(SPD_R_INTR_STAT) & 0x02)) {
733 if (ata_hwport->r_control & 0x01) {
734 M_PRINTF("Error: Command error while doing DMA.\n");
735 M_PRINTF("Error: Command error status 0x%02x, error 0x%02x.\n", ata_hwport->r_status, sceAtaGetError());
736 /* In v1.04, there was no check for ICRC. */
737 return ((sceAtaGetError() & ATA_ERR_ICRC) ? ATA_RES_ERR_ICRC : ATA_RES_ERR_IO);
738 } else {
739 M_PRINTF("Warning: Got command interrupt, but not an error.\n");
740 continue;
741 }
742 }
743
744 dma_stat = SPD_REG16(0x38) & 0x1f;
745
746 next_transfer:
747 count = (blkcount < dma_stat) ? blkcount : dma_stat;
748 nbytes = count * 512;
749 if ((res = SpdDmaTransfer(0, buf, (nbytes << 9) | 32, dir)) < 0)
750 return res;
751
752 buf = (void *)((u8 *)buf + nbytes);
753 blkcount -= count;
754 }
755
756 return 0;
757}
758#endif
759
760/* Export 7 */
761int sceAtaWaitResult(void)
762{
763#ifdef ATA_USE_DEV9
764 USE_SPD_REGS;
765 USE_ATA_REGS;
766#endif
767#ifdef ATA_USE_AIFDEV9
768 USE_AIF_ATA_REGS;
769#endif
770 ata_cmd_state_t *cmd_state = &atad_cmd_state;
771 u32 bits;
772 int res = 0, type = cmd_state->type;
773 u16 stat;
774
775 if (type == 1 || type == 6) { /* Non-data commands. */
776 WaitEventFlag(ata_evflg, ATA_EV_TIMEOUT | ATA_EV_COMPLETE, WEF_CLEAR | WEF_OR, &bits);
777 if (bits & ATA_EV_TIMEOUT) { /* Timeout. */
778 M_PRINTF("Error: ATA timeout on a non-data command.\n");
779 return ATA_RES_ERR_TIMEOUT;
780 }
781 } else if (type == 4) { /* DMA. */
782#ifdef ATA_USE_DEV9
783 int i;
784
785 if ((res = ata_dma_complete(cmd_state->buf, cmd_state->blkcount,
786 cmd_state->dir)) < 0)
787 goto finish;
788
789 for (i = 0; i < 100; i++)
790 if ((stat = SPD_REG16(SPD_R_INTR_STAT) & 0x01))
791 break;
792 if (!stat) {
793 SpdIntrEnable(SPD_INTR_ATA0);
794 WaitEventFlag(ata_evflg, ATA_EV_TIMEOUT | ATA_EV_COMPLETE, WEF_CLEAR | WEF_OR, &bits);
795 if (bits & ATA_EV_TIMEOUT) {
796 M_PRINTF("Error: ATA timeout on DMA completion, buffer stat %04x\n", SPD_REG16(0x38));
797 M_PRINTF("Error: istat %x, ienable %x\n", SPD_REG16(SPD_R_INTR_STAT), SPD_REG16(SPD_R_INTR_MASK));
798 res = ATA_RES_ERR_TIMEOUT;
799 }
800 }
801#endif
802#ifdef ATA_USE_AIFDEV9
803 res = -1;
804#endif
805 } else { /* PIO transfers. */
806 stat = ata_hwport->r_control;
807 if ((res = ata_wait_busy()) < 0)
808 goto finish;
809
810 /* Transfer each PIO data block. */
811 while ((int)(--cmd_state->blkcount) != -1) {
812 if ((res = ata_pio_transfer(cmd_state)) < 0)
813 goto finish;
814 if ((res = ata_wait_busy()) < 0)
815 goto finish;
816 }
817 }
818
819 if (res)
820 goto finish;
821
822 /* Wait until the device isn't busy. */
823 if (ata_hwport->r_status & ATA_STAT_BUSY)
824 res = ata_wait_busy();
825 if ((stat = ata_hwport->r_status) & ATA_STAT_ERR) {
826 M_PRINTF("Error: Command error: status 0x%02x, error 0x%02x.\n", stat, sceAtaGetError());
827 /* In v1.04, there was no check for ICRC. */
828 res = (sceAtaGetError() & ATA_ERR_ICRC) ? ATA_RES_ERR_ICRC : ATA_RES_ERR_IO;
829 }
830
831finish:
832 /* The command has completed (with an error or not), so clean things up. */
833 CancelAlarm(&ata_alarm_cb, NULL);
834#ifdef ATA_USE_DEV9
835 /* Turn off the LED. */
836 SpdSetLED(0);
837#endif
838
839 if (res)
840 M_PRINTF("error: ATA failed, %d\n", res);
841
842 return res;
843}
844
845/* Reset the ATA controller/bus. */
846static int ata_bus_reset(void)
847{
848#ifdef ATA_USE_DEV9
849 USE_SPD_REGS;
850 SPD_REG16(SPD_R_IF_CTRL) = SPD_IF_ATA_RESET;
851 DelayThread(100);
852 SPD_REG16(SPD_R_IF_CTRL) = 0; // Not present in v1.04.
853 SPD_REG16(SPD_R_IF_CTRL) = 0x48;
854 DelayThread(3000);
855#endif
856 return ata_wait_busy();
857}
858
859/* Export 5 */
860int sceAtaSoftReset(void)
861{
862#ifdef ATA_USE_DEV9
863 USE_ATA_REGS;
864#endif
865#ifdef ATA_USE_AIFDEV9
866 USE_AIF_ATA_REGS;
867#endif
868
869 if (ata_hwport->r_control & 0x80)
870 return ATA_RES_ERR_NOTREADY;
871
872 /* Disables device interrupt assertion and asserts SRST. */
873 ata_hwport->r_control = 6;
874 DelayThread(100);
875
876 /* Disable ATA interrupts. */
877 ata_hwport->r_control = 2;
878 DelayThread(3000);
879
880 return ata_wait_busy();
881}
882
883/* Export 17 */
884int sceAtaFlushCache(int device)
885{
886 int res;
887
888 if (!(res = sceAtaExecCmd(NULL, 1, 0, 0, 0, 0, 0, (device << 4) & 0xffff, (atad_devinfo[device].lba48 && !ata_dvrp_workaround) ? ATA_C_FLUSH_CACHE_EXT : ATA_C_FLUSH_CACHE)))
889 res = sceAtaWaitResult();
890
891 return res;
892}
893
894/* Export 13 */
895int sceAtaIdle(int device, int period)
896{
897 int res;
898
899 if (!(res = sceAtaExecCmd(NULL, 1, 0, period & 0xff, 0, 0, 0, (device << 4) & 0xffff, ATA_C_IDLE)))
900 res = sceAtaWaitResult();
901
902 return res;
903}
904
905static int ata_device_identify(int device, void *info)
906{
907 int res;
908
909 if (!(res = sceAtaExecCmd(info, 1, 0, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_IDENTIFY_DEVICE)))
910 res = sceAtaWaitResult();
911
912 return res;
913}
914
915static int ata_device_pkt_identify(int device, void *info)
916{
917 int res;
918
919 res = sceAtaExecCmd(info, 1, 0, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_IDENTIFY_PACKET_DEVICE);
920 if (!res)
921 return sceAtaWaitResult();
922 return res;
923}
924
925/* Export 14 */
926int sceAtaGetSceId(int device, void *data)
927{
928 int res;
929
930 if (!(res = sceAtaExecCmd(data, 1, ATA_SCE_IDENTIFY_DRIVE, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL)))
931 res = sceAtaWaitResult();
932
933 return res;
934}
935
936static int ata_device_smart_enable(int device)
937{
938 int res;
939
940 if (!(res = sceAtaExecCmd(NULL, 1, ATA_S_SMART_ENABLE_OPERATIONS, 0, 0, 0x4f, 0xc2, (device << 4) & 0xffff, ATA_C_SMART)))
941 res = sceAtaWaitResult();
942
943 return res;
944}
945
946/* Export 16 */
947int sceAtaSmartSaveAttr(int device)
948{
949 int res;
950
951 if (!(res = sceAtaExecCmd(NULL, 1, ATA_S_SMART_SAVE_ATTRIBUTE_VALUES, 0, 0, 0x4f, 0xc2, (device << 4) & 0xffff, ATA_C_SMART)))
952 res = sceAtaWaitResult();
953
954 return res;
955}
956
957/* Export 15 */
958int sceAtaSmartReturnStatus(int device)
959{
960 USE_ATA_REGS;
961 int res;
962
963 res = sceAtaExecCmd(NULL, 1, ATA_S_SMART_RETURN_STATUS, 0, 0, 0x4f, 0xc2, (device << 4) & 0xffff, ATA_C_SMART);
964 if (res)
965 return res;
966
967 res = sceAtaWaitResult();
968 if (res)
969 return res;
970
971 /* Check to see if the report exceeded the threshold. */
972 if (((ata_hwport->r_lcyl & 0xFF) != 0x4f) || ((ata_hwport->r_hcyl & 0xFF) != 0xc2)) {
973 M_PRINTF("Error: SMART report exceeded threshold.\n");
974 return 1;
975 }
976
977 return 0;
978}
979
980/* Set features - set transfer mode. */
981static int ata_device_set_transfer_mode(int device, int type, int mode)
982{
983 int res;
984
985 res = sceAtaExecCmd(NULL, 1, 3, (type | mode) & 0xff, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SET_FEATURES);
986 if (res)
987 return res;
988
989 res = sceAtaWaitResult();
990 if (res)
991 return res;
992
993 switch (type) {
994#ifdef ATA_USE_DEV9
995#ifdef ATA_MWDMA_MODES
996 case ATA_XFER_MODE_MDMA:
997 ata_multiword_dma_mode(mode);
998 break;
999#endif
1000 case ATA_XFER_MODE_UDMA:
1001 ata_ultra_dma_mode(mode);
1002 break;
1003 case ATA_XFER_MODE_PIO:
1004 ata_pio_mode(mode);
1005 break;
1006#endif
1007#ifdef ATA_USE_AIFDEV9
1008 case ATA_XFER_MODE_PIO:
1009 aif_tune_drive(0, mode);
1010 break;
1011#endif
1012 }
1013
1014 return 0;
1015}
1016
1017/* Export 9 */
1018/* Note: this can only support DMA modes, due to the commands issued. */
1019int sceAtaDmaTransfer(int device, void *buf, u32 lba, u32 nsectors, int dir)
1020{
1021 return ata_device_sector_io64(device, buf, (u64)lba, nsectors, dir);
1022}
1023
1024int ata_device_sector_io64(int device, void *buf, u64 lba, u32 nsectors, int dir)
1025{
1026 USE_SPD_REGS;
1027 int res = 0, retries;
1028 u16 sector, lcyl, hcyl, select, command, len;
1029
1030 while (res == 0 && nsectors > 0) {
1031
1032 if (atad_devinfo[device].lba48 && (ata_dvrp_workaround ? (lba >= atad_devinfo[device].total_sectors) : 1)) {
1033 /* Setup for 48-bit LBA. */
1034 len = (u16)((nsectors > 65536) ? 65536 : nsectors); /* 0 means 65536 in LBA48 */
1035
1036 /* Combine bits 24-31 and bits 0-7 of lba into sector. */
1037 sector = ((lba >> 16) & 0xff00) | (lba & 0xff);
1038 lcyl = ((lba >> 24) & 0xff00) | ((lba >> 8) & 0xff);
1039 hcyl = ((lba >> 32) & 0xff00) | ((lba >> 16) & 0xff);
1040
1041 /* In v1.04, LBA was enabled here. */
1042 select = (device << 4) & 0xffff;
1043 command = (dir == 1) ? ATA_C_WRITE_DMA_EXT : ATA_C_READ_DMA_EXT;
1044 } else {
1045 /* Setup for 28-bit LBA. */
1046 len = (nsectors > 256) ? 256 : nsectors;
1047 sector = lba & 0xff;
1048 lcyl = (lba >> 8) & 0xff;
1049 hcyl = (lba >> 16) & 0xff;
1050
1051 /* In v1.04, LBA was enabled here. */
1052 select = ((device << 4) | ((lba >> 24) & 0xf)) & 0xffff;
1053 command = (dir == 1) ? ATA_C_WRITE_DMA : ATA_C_READ_DMA;
1054 }
1055
1056 for (retries = 3; retries > 0; retries--) {
1057#ifdef ATA_USE_DEV9
1058#ifdef ATA_GAMESTAR_WORKAROUND
1059 /* Due to the retry loop, put this call (for the GameStar workaround) here instead of the old location. */
1060 if (ata_gamestar_workaround)
1061 ata_set_dir(dir);
1062#endif
1063#endif
1064
1065 if ((res = sceAtaExecCmd(buf, len, 0, len, sector, lcyl, hcyl, select, command)) != 0)
1066 break;
1067
1068#ifdef ATA_USE_DEV9
1069#ifdef ATA_GAMESTAR_WORKAROUND
1070 if (!ata_gamestar_workaround)
1071 ata_set_dir(dir);
1072#else
1073 /* Set up (part of) the transfer here. In v1.04, this was called at the top of the outer loop. */
1074 ata_set_dir(dir);
1075#endif
1076#endif
1077
1078 res = sceAtaWaitResult();
1079
1080 /* In v1.04, this was not done. Neither was there a mechanism to retry if a non-permanent error occurs. */
1081 SPD_REG16(SPD_R_IF_CTRL) &= ~SPD_IF_DMA_ENABLE;
1082
1083 if (res != ATA_RES_ERR_ICRC)
1084 break;
1085 }
1086
1087 buf = (void *)((u8 *)buf + len * 512);
1088 lba += len;
1089 nsectors -= len;
1090 }
1091
1092 return res;
1093}
1094
1095static void ata_get_security_status(int device, ata_devinfo_t *devinfo, u16 *param)
1096{
1097 if (ata_device_identify(device, param) == 0)
1098 devinfo[device].security_status = param[ATA_ID_SECURITY_STATUS];
1099}
1100
1101/* Export 10 */
1102int sceAtaSecuritySetPassword(int device, void *password)
1103{
1104 ata_devinfo_t *devinfo = atad_devinfo;
1105 u16 *param = ata_param;
1106 int res;
1107
1108 if (devinfo[device].security_status & ATA_F_SEC_ENABLED)
1109 return 0;
1110
1111 memset(param, 0, 512);
1112 memcpy(param + 1, password, 32);
1113
1114 res = sceAtaExecCmd(param, 1, ATA_SCE_SECURITY_SET_PASSWORD, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL);
1115 if (res == 0)
1116 res = sceAtaWaitResult();
1117
1118 ata_get_security_status(device, devinfo, param);
1119 return res;
1120}
1121
1122/* Export 11 */
1123int sceAtaSecurityUnLock(int device, void *password)
1124{
1125 ata_devinfo_t *devinfo = atad_devinfo;
1126 u16 *param = ata_param;
1127 int res;
1128
1129 if (!(devinfo[device].security_status & ATA_F_SEC_LOCKED))
1130 return 0;
1131
1132 memset(param, 0, 512);
1133 memcpy(param + 1, password, 32);
1134
1135 if ((res = sceAtaExecCmd(param, 1, ATA_SCE_SECURITY_UNLOCK, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL)) != 0)
1136 return res;
1137 if ((res = sceAtaWaitResult()) != 0)
1138 return res;
1139
1140 /* Check to see if the drive was actually unlocked. */
1141 ata_get_security_status(device, devinfo, param);
1142 if (devinfo[device].security_status & ATA_F_SEC_LOCKED)
1143 return ATA_RES_ERR_LOCKED;
1144
1145 return 0;
1146}
1147
1148/* Export 12 */
1149int sceAtaSecurityEraseUnit(int device)
1150{
1151 ata_devinfo_t *devinfo = atad_devinfo;
1152 int res;
1153
1154 if (!(devinfo[device].security_status & ATA_F_SEC_ENABLED) || !(devinfo[device].security_status & ATA_F_SEC_LOCKED))
1155 return 0;
1156
1157 /* First send the mandatory ERASE PREPARE command. */
1158 if ((res = sceAtaExecCmd(NULL, 1, ATA_SCE_SECURITY_ERASE_PREPARE, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL)) != 0)
1159 goto finish;
1160 if ((res = sceAtaWaitResult()) != 0)
1161 goto finish;
1162
1163 if ((res = sceAtaExecCmd(NULL, 1, ATA_SCE_SECURITY_ERASE_UNIT, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL)) == 0)
1164 res = sceAtaWaitResult();
1165
1166finish:
1167 ata_get_security_status(device, devinfo, NULL);
1168 return res;
1169}
1170
1171static void ata_device_probe(ata_devinfo_t *devinfo)
1172{
1173#ifdef ATA_USE_DEV9
1174 USE_ATA_REGS;
1175#endif
1176#ifdef ATA_USE_AIFDEV9
1177 USE_AIF_ATA_REGS;
1178#endif
1179 u16 nsector, sector, lcyl, hcyl;
1180
1181 devinfo->exists = 0;
1182 devinfo->has_packet = 2;
1183
1184 if (ata_hwport->r_control & 0x88)
1185 return;
1186
1187 nsector = ata_hwport->r_nsector & 0xff;
1188 sector = ata_hwport->r_sector & 0xff;
1189 lcyl = ata_hwport->r_lcyl & 0xff;
1190 hcyl = ata_hwport->r_hcyl & 0xff;
1191 (void)ata_hwport->r_select;
1192
1193 if ((nsector != 1) || (sector != 1))
1194 return;
1195 devinfo->exists = 1;
1196
1197 if ((lcyl == 0x00) && (hcyl == 0x00))
1198 devinfo->has_packet = 0;
1199 else if ((lcyl == 0x14) && (hcyl == 0xeb))
1200 devinfo->has_packet = 1;
1201
1202 /* Seems to be for ensuring that there is a device connected.
1203 Not sure why this has to be done, but is present in v2.4. */
1204 ata_hwport->r_lcyl = 0x55;
1205 ata_hwport->r_hcyl = 0xaa;
1206 lcyl = ata_hwport->r_lcyl & 0xff;
1207 hcyl = ata_hwport->r_hcyl & 0xff;
1208
1209 if ((lcyl != 0x55) || (hcyl != 0xaa))
1210 devinfo->exists = 0;
1211}
1212
1213static int ata_init_devices(ata_devinfo_t *devinfo)
1214{
1215#ifdef ATA_USE_DEV9
1216 USE_ATA_REGS;
1217#endif
1218#ifdef ATA_USE_AIFDEV9
1219 USE_AIF_ATA_REGS;
1220#endif
1221 int i, res;
1222 u32 total_sectors_nonlba48, total_sectors_lba48;
1223
1224 if ((res = sceAtaSoftReset()) != 0)
1225 return res;
1226
1227 ata_device_probe(&devinfo[0]);
1228 if (!devinfo[0].exists) {
1229 M_PRINTF("Error: Unable to detect HDD 0.\n");
1230 devinfo[1].exists = 0;
1231 return ATA_RES_ERR_NODEV; // Returns 0 in v1.04.
1232 }
1233
1234 /* If there is a device 1, grab it's info too. */
1235 if ((res = ata_device_select(1)) != 0)
1236 return res;
1237 if (ata_hwport->r_control & 0xff)
1238 ata_device_probe(&devinfo[1]);
1239 else
1240 devinfo[1].exists = 0;
1241
1242#ifdef ATA_USE_DEV9
1243 ata_pio_mode(0); // PIO mode is set here, in late ATAD versions.
1244#endif
1245
1246 for (i = 0; i < 2; i++) {
1247 if (!devinfo[i].exists)
1248 continue;
1249
1250 /* Send the IDENTIFY DEVICE command. if it doesn't succeed
1251 devinfo is disabled. */
1252 if (!devinfo[i].has_packet) {
1253 res = ata_device_identify(i, ata_param);
1254 devinfo[i].exists = (res == 0);
1255 } else if (devinfo[i].has_packet == 1) {
1256 /* If it's a packet device, send the IDENTIFY PACKET
1257 DEVICE command. */
1258 res = ata_device_pkt_identify(i, ata_param);
1259 devinfo[i].exists = (res == 0);
1260 }
1261 /* Otherwise, do nothing if has_packet = 2. */
1262
1263 /* This next section is HDD-specific: if no device or it's a
1264 packet (ATAPI) device, we're done. */
1265 if (!devinfo[i].exists || devinfo[i].has_packet)
1266 continue;
1267
1268 /* This section is to detect whether the HDD supports 48-bit LBA
1269 (IDENITFY DEVICE bit 10 word 83) and get the total sectors from
1270 either words(61:60) for 28-bit or words(103:100) for 48-bit. */
1271 devinfo[i].lba48 = (ata_param[ATA_ID_COMMAND_SETS_SUPPORTED] & 0x0400) != 0;
1272
1273 /* Save the total sector counts before we overwrite ata_param with the value of Sony identify drive command. */
1274 total_sectors_nonlba48 = (ata_param[ATA_ID_SECTOTAL_HI] << 16) | ata_param[ATA_ID_SECTOTAL_LO];
1275 if (ata_param[ATA_ID_48BIT_SECTOTAL_HI]) {
1276 total_sectors_lba48 = 0xffffffff;
1277 } else {
1278 total_sectors_lba48 = (ata_param[ATA_ID_48BIT_SECTOTAL_MI] << 16) | ata_param[ATA_ID_48BIT_SECTOTAL_LO];
1279 }
1280
1281 devinfo[i].security_status = ata_param[ATA_ID_SECURITY_STATUS];
1282
1283#ifdef ATA_USE_DEV9
1284 u8 maxUDMA = 4;
1285#ifdef ATA_ENABLE_MAXUDMA
1286 maxUDMA = 6;
1287#endif
1288
1289 /* Ultra DMA mode 4. */
1290 u8 udmaMode = 4;
1291 /* Check the highest UDMA mode supported */
1292 for (int j = maxUDMA; j >= 0; j--) {
1293 /* Check if the current UDMA mode is supported, store it and exit from the loop. */
1294 if (((ata_param[ATA_ID_UDMA_CONTROL] & 0xFF) & (1 << j)) != 0) {
1295 udmaMode = j;
1296 break;
1297 }
1298 }
1299 ata_device_set_transfer_mode(i, ATA_XFER_MODE_UDMA, udmaMode);
1300#endif
1301#ifdef ATA_USE_AIFDEV9
1302 /* PIO mode 4. */
1303 ata_device_set_transfer_mode(i, ATA_XFER_MODE_PIO, 4);
1304#endif
1305 ata_device_smart_enable(i);
1306 /* Set standby timer to 21min 15s. */
1307 sceAtaIdle(i, 0xff);
1308
1309 if (devinfo[i].lba48) {
1310 /* If this device is emulated through the DVRP, use the non-48-bit LBA size. */
1311 if (ata_dvrp_workaround) {
1312 devinfo[i].total_sectors = total_sectors_nonlba48;
1313 } else {
1314 devinfo[i].total_sectors = total_sectors_lba48;
1315 }
1316 devinfo[i].total_sectors_lba48 = total_sectors_lba48;
1317 } else {
1318 devinfo[i].total_sectors = total_sectors_nonlba48;
1319 devinfo[i].total_sectors_lba48 = total_sectors_nonlba48;
1320 }
1321
1322 /* Call the proprietary identify command. */
1323#ifdef ATA_SCE_AUTH_HDD
1324 if (sceAtaGetSceId(i, ata_param) != 0) {
1325 M_PRINTF("error: This is not SCE genuine HDD.\n");
1326 memset(&devinfo[i], 0, sizeof(devinfo[i]));
1327 }
1328#endif
1329
1330#ifdef ATA_ENABLE_BDM
1331 g_ata_bd[i].sectorCount = devinfo[i].total_sectors_lba48;
1332 bdm_connect_bd(&g_ata_bd[i]);
1333#endif
1334 }
1335 return 0;
1336}
1337
1338/* Export 4 */
1339ata_devinfo_t *sceAtaInit(int device)
1340{
1341 if (!ata_devinfo_init) {
1342 ata_devinfo_init = 1;
1343 if (ata_bus_reset() || ata_init_devices(atad_devinfo))
1344 return NULL;
1345 }
1346
1347 return &atad_devinfo[device];
1348}
1349
1350#ifdef ATA_USE_DEV9
1351static void ata_set_dir(int dir)
1352{
1353 USE_SPD_REGS;
1354 u16 val;
1355
1356 SPD_REG16(0x38) = 3;
1357 val = SPD_REG16(SPD_R_IF_CTRL) & 1;
1358 val |= (dir == ATA_DIR_WRITE) ? 0x4c : 0x4e;
1359 SPD_REG16(SPD_R_IF_CTRL) = val;
1360#ifdef ATA_GAMESTAR_WORKAROUND
1361 SPD_REG16(SPD_R_XFR_CTRL) = dir | (ata_gamestar_workaround ? 0x86 : 0x6);
1362#else
1363 SPD_REG16(SPD_R_XFR_CTRL) = dir | 0x6; // In v1.04, DMA was enabled here (0x86 instead of 0x6)
1364#endif
1365}
1366
1367static void ata_pio_mode(int mode)
1368{
1369 USE_SPD_REGS;
1370 (void)mode;
1371#ifdef ATA_ALL_PIO_MODES
1372 u16 val;
1373
1374 switch (mode) {
1375 case 1:
1376 val = 0x72;
1377 break;
1378 case 2:
1379 val = 0x32;
1380 break;
1381 case 3:
1382 val = 0x24;
1383 break;
1384 case 4:
1385 val = 0x23;
1386 break;
1387 default:
1388 val = 0x92;
1389 }
1390
1391 SPD_REG16(SPD_R_PIO_MODE) = val;
1392#else
1393 /* In the late ATAD versions, PIO mode 0 is always used if PIO mode is utilized. */
1394 SPD_REG16(SPD_R_PIO_MODE) = 0x92;
1395#endif
1396}
1397
1398#ifdef ATA_MWDMA_MODES
1399static void ata_multiword_dma_mode(int mode)
1400{
1401 USE_SPD_REGS;
1402 u16 val;
1403
1404 switch (mode) {
1405 case 1:
1406 val = 0x45;
1407 break;
1408 case 2:
1409 val = 0x24;
1410 break;
1411 default:
1412 val = 0xff;
1413 }
1414
1415 SPD_REG16(SPD_R_MWDMA_MODE) = val;
1416 SPD_REG16(SPD_R_IF_CTRL) = (SPD_REG16(SPD_R_IF_CTRL) & 0xfffe) | 0x48;
1417}
1418#endif
1419
1420static void ata_ultra_dma_mode(int mode)
1421{
1422 USE_SPD_REGS;
1423 u16 val;
1424
1425 switch (mode) {
1426 case 1:
1427 val = 0x85;
1428 break;
1429 case 2:
1430 val = 0x63;
1431 break;
1432 case 3:
1433 val = 0x62;
1434 break;
1435 case 4:
1436 val = 0x61;
1437 break;
1438 default:
1439 val = 0xa7;
1440 }
1441
1442 SPD_REG16(SPD_R_UDMA_MODE) = val;
1443 SPD_REG16(SPD_R_IF_CTRL) |= 0x49;
1444}
1445#endif
1446
1447#ifdef ATA_USE_AIFDEV9
1448static void aif_tune_drive(int unit, int mode)
1449{
1450 USE_AIF_REGS;
1451 unsigned int use_iordy, value;
1452
1453 use_iordy = 1;
1454 value = (use_iordy << 3) | mode;
1455 M_PRINTF("AIF HDD: tune unit%d, mode=%u\n", unit, value);
1456
1457 switch (unit) {
1458 case 0:
1459 aif_regs[AIF_ATA_TCFG] = (aif_regs[AIF_ATA_TCFG] & 0xf0) + value;
1460 break;
1461 case 1:
1462 aif_regs[AIF_ATA_TCFG] = (aif_regs[AIF_ATA_TCFG] & 0x0f) + (value << 4);
1463 break;
1464 }
1465}
1466#endif
1467
1468/* Export 18 */
1469int sceAtaIdleImmediate(int device)
1470{
1471 int res;
1472
1473 if (!(res = sceAtaExecCmd(NULL, 1, 0, 0, 0, 0, 0, (device << 4) & 0xFFFF, ATA_C_IDLE_IMMEDIATE)))
1474 res = sceAtaWaitResult();
1475
1476 return res;
1477}
1478
1479static int ata_device_standby_immediate(int device)
1480{
1481 int res;
1482
1483 if (!(res = sceAtaExecCmd(NULL, 1, 0, 0, 0, 0, 0, (device << 4) & 0xFFFF, ATA_C_STANDBY_IMMEDIATE)))
1484 res = sceAtaWaitResult();
1485
1486 return res;
1487}
1488
1489static void ata_shutdown_cb(void)
1490{
1491 int i;
1492
1493 for (i = 0; i < 2; i++) {
1494 if (atad_devinfo[i].exists)
1495 ata_device_standby_immediate(i);
1496 }
1497}
1498
1499#ifdef ATA_ENABLE_BDM
1500//
1501// Block device interface
1502//
1503static int ata_bd_read(struct block_device *bd, u64 sector, void *buffer, u16 count)
1504{
1505 if (ata_device_sector_io64(bd->devNr, buffer, sector, count, ATA_DIR_READ) != 0) {
1506 return -EIO;
1507 }
1508
1509 return count;
1510}
1511
1512static int ata_bd_write(struct block_device *bd, u64 sector, const void *buffer, u16 count)
1513{
1514 if (ata_device_sector_io64(bd->devNr, (void *)buffer, sector, count, ATA_DIR_WRITE) != 0) {
1515 return -EIO;
1516 }
1517
1518 return count;
1519}
1520
1521static void ata_bd_flush(struct block_device *bd)
1522{
1523 sceAtaFlushCache(bd->devNr);
1524}
1525
1526static int ata_bd_stop(struct block_device *bd)
1527{
1528 ata_device_standby_immediate(bd->devNr);
1529
1530 return 0;
1531}
1532#endif
_ata_devinfo::security_status
u32 security_status
Definition xatapi.c:44
_ata_devinfo::lba48
u32 lba48
Definition xatapi.c:45
_ata_devinfo::exists
s32 exists
Definition xatapi.c:41
_ata_devinfo::total_sectors
u32 total_sectors
Definition xatapi.c:43
_ata_devinfo::has_packet
s32 has_packet
Definition xatapi.c:42
_ata_devinfo::total_sectors_lba48
u32 total_sectors_lba48
Definition atad.h:39
_ata_devinfo
Definition xatapi.c:40
block_device
Definition bdm.h:22
EIO
#define EIO
Definition errno.h:29
irx_export_table
Definition irx.h:90
_ata_cmd_info
Definition ps2atad.c:88
_ata_cmd_state
Definition xatapi.c:22
s_info
Definition xprintf.c:78
_iop_sys_clock
Definition thbase.h:88
EA_SINGLE
#define EA_SINGLE
Definition thevent.h:33
iop_event_t
Definition thevent.h:38
count
u32 count
start sector of fragmented bd/file
Definition usbhdfsd-common.h:1