#include <tamtypes.h>

Include dependency graph for speedregs.h:

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Macros
#define	SPD_REGBASE 0xb0000000

#define	USE_SPD_REGS volatile u8 spd_regbase = (volatile u8 )SPD_REGBASE

#define	SPD_REG8(offset) ((volatile u8 )(spd_regbase + (offset)))

#define	SPD_REG16(offset) ((volatile u16 )(spd_regbase + (offset)))

#define	SPD_REG32(offset) ((volatile u32 )(spd_regbase + (offset)))

#define	SPD_R_REV 0x00

#define	SPD_R_REV_1 0x02

#define	SPD_R_REV_3 0x04

#define	SPD_CAPS_SMAP (1 << 0)

#define	SPD_CAPS_ATA (1 << 1)

#define	SPD_CAPS_UART (1 << 3)

#define	SPD_CAPS_DVR (1 << 4)

#define	SPD_CAPS_FLASH (1 << 5)

#define	SPD_R_REV_8 0x0e

#define	SPD_R_DMA_CTRL 0x24

#define	SPD_R_INTR_STAT 0x28

#define	SPD_R_INTR_MASK 0x2a

#define	SPD_INTR_ATA0 (1 << 0)

#define	SPD_INTR_ATA1 (1 << 1)

#define	SPD_INTR_ATA (SPD_INTR_ATA0 \| SPD_INTR_ATA1)

#define	SPD_INTR_DVR (1 << 9)

#define	SPD_INTR_UART (1 << 12)

#define	SPD_R_PIO_DIR 0x2c

#define	SPD_R_PIO_DATA 0x2e

#define	SPD_PP_DOUT (1 << 4)

#define	SPD_PP_DIN (1 << 5)

#define	SPD_PP_SCLK (1 << 6)

#define	SPD_PP_CSEL (1 << 7)

#define	SPD_PP_OP_READ 2

#define	SPD_PP_OP_WRITE 1

#define	SPD_PP_OP_EWEN 0

#define	SPD_PP_OP_EWDS 0

#define	SPD_R_XFR_CTRL 0x32

#define	SPD_R_IF_CTRL 0x64

#define	SPD_IF_ATA_RESET 0x80

#define	SPD_IF_DMA_ENABLE 0x04

#define	SPD_R_PIO_MODE 0x70

#define	SPD_R_MWDMA_MODE 0x72

#define	SPD_R_UDMA_MODE 0x74

Detailed Description

SPEED (ASIC on SMAP) register definitions.

Definition in file speedregs.h.

Macro Definition Documentation

◆ SPD_REGBASE

#define SPD_REGBASE 0xb0000000

Definition at line 24 of file speedregs.h.

◆ USE_SPD_REGS

#define USE_SPD_REGS volatile u8 *spd_regbase = (volatile u8 *)SPD_REGBASE

Definition at line 27 of file speedregs.h.

◆ SPD_REG8

#define SPD_REG8 ( offset ) (*(volatile u8 *)(spd_regbase + (offset)))

Definition at line 29 of file speedregs.h.

◆ SPD_REG16

#define SPD_REG16 ( offset ) (*(volatile u16 *)(spd_regbase + (offset)))

Definition at line 30 of file speedregs.h.

◆ SPD_REG32

#define SPD_REG32 ( offset ) (*(volatile u32 *)(spd_regbase + (offset)))

Definition at line 31 of file speedregs.h.

◆ SPD_R_REV

#define SPD_R_REV 0x00

Definition at line 33 of file speedregs.h.

◆ SPD_R_REV_1

#define SPD_R_REV_1 0x02

Definition at line 34 of file speedregs.h.

◆ SPD_R_REV_3

#define SPD_R_REV_3 0x04

Definition at line 35 of file speedregs.h.

◆ SPD_CAPS_SMAP

#define SPD_CAPS_SMAP (1 << 0)

Definition at line 36 of file speedregs.h.

◆ SPD_CAPS_ATA

#define SPD_CAPS_ATA (1 << 1)

Definition at line 37 of file speedregs.h.

◆ SPD_CAPS_UART

#define SPD_CAPS_UART (1 << 3)

Definition at line 38 of file speedregs.h.

◆ SPD_CAPS_DVR

#define SPD_CAPS_DVR (1 << 4)

Definition at line 39 of file speedregs.h.

◆ SPD_CAPS_FLASH

#define SPD_CAPS_FLASH (1 << 5)

Definition at line 40 of file speedregs.h.

◆ SPD_R_REV_8

#define SPD_R_REV_8 0x0e

Definition at line 41 of file speedregs.h.

◆ SPD_R_DMA_CTRL

#define SPD_R_DMA_CTRL 0x24

Definition at line 43 of file speedregs.h.

◆ SPD_R_INTR_STAT

#define SPD_R_INTR_STAT 0x28

Definition at line 44 of file speedregs.h.

◆ SPD_R_INTR_MASK

#define SPD_R_INTR_MASK 0x2a

Definition at line 45 of file speedregs.h.

◆ SPD_INTR_ATA0

#define SPD_INTR_ATA0 (1 << 0)

Definition at line 46 of file speedregs.h.

◆ SPD_INTR_ATA1

#define SPD_INTR_ATA1 (1 << 1)

Definition at line 47 of file speedregs.h.

◆ SPD_INTR_ATA

#define SPD_INTR_ATA (SPD_INTR_ATA0 | SPD_INTR_ATA1)

Definition at line 48 of file speedregs.h.

◆ SPD_INTR_DVR

#define SPD_INTR_DVR (1 << 9)

Definition at line 50 of file speedregs.h.

◆ SPD_INTR_UART

#define SPD_INTR_UART (1 << 12)

Definition at line 51 of file speedregs.h.

◆ SPD_R_PIO_DIR

#define SPD_R_PIO_DIR 0x2c

Definition at line 52 of file speedregs.h.

◆ SPD_R_PIO_DATA

#define SPD_R_PIO_DATA 0x2e

Definition at line 53 of file speedregs.h.

◆ SPD_PP_DOUT

#define SPD_PP_DOUT (1 << 4)

Data output, read port

Definition at line 55 of file speedregs.h.

◆ SPD_PP_DIN

#define SPD_PP_DIN (1 << 5)

Data input, write port

Definition at line 57 of file speedregs.h.

◆ SPD_PP_SCLK

#define SPD_PP_SCLK (1 << 6)

Clock, write port

Definition at line 59 of file speedregs.h.

◆ SPD_PP_CSEL

#define SPD_PP_CSEL (1 << 7)

Chip select, write port

Definition at line 61 of file speedregs.h.

◆ SPD_PP_OP_READ

#define SPD_PP_OP_READ 2

Definition at line 63 of file speedregs.h.

◆ SPD_PP_OP_WRITE

#define SPD_PP_OP_WRITE 1

Definition at line 64 of file speedregs.h.

◆ SPD_PP_OP_EWEN

#define SPD_PP_OP_EWEN 0

Definition at line 65 of file speedregs.h.

◆ SPD_PP_OP_EWDS

#define SPD_PP_OP_EWDS 0

Definition at line 66 of file speedregs.h.

◆ SPD_R_XFR_CTRL

#define SPD_R_XFR_CTRL 0x32

Definition at line 68 of file speedregs.h.

◆ SPD_R_IF_CTRL

#define SPD_R_IF_CTRL 0x64

Definition at line 69 of file speedregs.h.

◆ SPD_IF_ATA_RESET

#define SPD_IF_ATA_RESET 0x80

Definition at line 70 of file speedregs.h.

◆ SPD_IF_DMA_ENABLE

#define SPD_IF_DMA_ENABLE 0x04

Definition at line 71 of file speedregs.h.

◆ SPD_R_PIO_MODE

#define SPD_R_PIO_MODE 0x70

Definition at line 72 of file speedregs.h.

◆ SPD_R_MWDMA_MODE

#define SPD_R_MWDMA_MODE 0x72

Definition at line 73 of file speedregs.h.

◆ SPD_R_UDMA_MODE

#define SPD_R_UDMA_MODE 0x74

Definition at line 74 of file speedregs.h.

Macros